190322 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
Performance-based grouping of storage devices in a storage system
#302Performance-based grouping of storage devices in a storage system
#303Power management message bus system
#304Memory system with region-specific memory access scheduling
#305DISAGGREGATED MEMORY APPLIANCE
#306Clock generation for timing communications with ranks of memory devices
#307Control of page access in memory
#308Data processing method, apparatus, and system
#309Computer architecture having selectable, parallel and serial communication channels between processors and memory
#310Method of controlling erase operation of a memory and memory system implementing the same
#311Memory controllers, memory systems, solid state drives and methods for processing a number of commands
#312Prioritized Memory Reads
#313Memory controller, information processing apparatus, and method of controlling memory controller
#314Resource management for peripheral component interconnect-express domains
#315NVM express controller for remote access of memory and I/O over Ethernet-type networks
#316Scheduling memory accesses using an efficient row burst value
#317Programmable latency count to achieve higher memory bandwidth
#318Memory system with improved efficiency of data transfer between host, buffer, and nonvolatile memory
#319Method and apparatus for sending data from multiple sources over a communications bus
#320Method of accessing on-chip read only memory and computer system thereof
#321Speculative memory controller
#322MEMORY SYSTEM
#323Memory controllers, memory systems, solid state drives and methods for processing a number of commands
#324Apparatuses and methods for variable latency memory operations
#325Memory systems and methods including training, data organizing, and/or shadowing
#326Control of page access in memory
#327Mitigate flash write latency and bandwidth limitation by preferentially storing frequently written sectors in cache memory during a databurst
#328Memory buffering system that improves read/write performance and provides low latency for mobile systems
#329Efficient suspend-resume operation in memory devices
#330Variable read latency on a serial memory bus
#331Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
#332Arbitrating memory accesses via a shared memory fabric
#333Storage controller selecting system, storage controller selecting method, and recording medium
#334Apparatuses and methods for memory operations having variable latencies
#335Input/output traffic backpressure prediction
#336Input/output traffic backpressure prediction
#337Data access method of a memory device
#338Memory timing optimization using pattern based signaling modulation
#339Data processing apparatus and a method for setting priority levels for transactions
#340Memory subsystem and computer system
#341Mirroring memory commands to memory devices
#342Quality of service management
#343Clock generation for timing communications with ranks of memory devices
#344Command decoding method and circuit of the same
#345Control of page access in memory
#346Memory configured to provide simultaneous read/write access to multiple banks
#347DEVICE AND DATA PROCESSING SYSTEM
#348Quality of Service Arbitration Method and Quality of Service Arbiter Thereof
#349Computer system and storage management method
#350Semiconductor device having PDA function
#351Variable read latency on a serial memory bus
#352Method and apparatus for load-based prefetch access
#353Quality of service management
#354Memory arbiter with latency guarantees for multiple ports
#355Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
#356Hierarchical memory arbitration technique for disparate sources
#357Memory controllers, memory systems, solid state drives and methods for processing a number of commands
#358Apparatus and method for buffered write commands in a memory
#359Information processing apparatus and information processing method
#360Mitigate flash write latency and bandwidth limitation with a sector-based write activity log
#361Memory throughput increase via fine granularity of precharge management
#362Nonvolatile memory, memory controller, nonvolatile memory accessing method, and program
#363PROCESSOR, DATA PROCESSING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE PROCESSOR
#364Memory hub with internal cache and/or memory access prediction
#365METHOD AND SYSTEM FOR RESOLVING INTEROPERABILITY OF MULTIPLE TYPES OF DUAL IN-LINE MEMORY MODULES
#366Controlling latency and power consumption in a memory
#367INTEGRATED CIRCUIT DEVICE COMPRISES AN INTERFACE TO TRANSMIT A FIRST CODE, A STROBE SIGNAL AFTER A DELAY AND DATA TO A DYNAMIC RANDOM ACCESS MEMORY (DRAM)
#368Memory System
#369Method and apparatus for sending data from multiple sources over a communications bus
#370Semiconductor device
#371Systems and methods for resource controlling
#372Memory controllers, memory systems, solid state drives and methods for processing a number of commands
#373MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOL
#374Memory controller and data processing system
#375Bandwidth adaptive memory compression
#376Memory interface with reduced read-write turnaround delay
#377Quantum burst arbiter and memory controller
#378Methods of bus arbitration for low power memory access
#379Sorting movable memory hierarchies in a computer system
#380Variable read latency on a serial memory bus
#381Memory interface having extended strobe burst for read timing calibration
#382Memory hub with internal cache and/or memory access prediction
#383Command decoding method and circuit of the same
#384Memory controller and associated control method
#385Variable read latency on a serial memory bus
#386Arbitrated access to memory shared by a processor and a data flow
#387Processing system with external memory access control
#388Data access method of a memory device
#389Data processing apparatus and a method for setting priority levels for transactions
#390Iterative write pausing techniques to improve read latency of memory systems
#391MEMORY CONTROL CIRCUIT AND MEMORY CONTROL METHOD
#392Control of page access in memory
#393Information processing system and data transfer method
#394Method and apparatus for sending data from multiple sources over a communications bus
#395Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
#396Hierarchical memory arbitration technique for disparate sources
#397Memory controllers, memory systems, solid state drives and methods for processing a number of commands
#398Apparatus and method for buffered write commands in a memory
#399Multi-bank multi-port architecture
#400IN-DRAM CYCLE-BASED LEVELIZATION
#401Systems and methods for improving the performance of non-volatile memory operations
#402Quality of service management
#403MEMORY ACCESS CONTROL APPARATUS
#404Memory controller and data processing system
#405Memory system with improved efficiency of data transfer between host, buffer, and nonvolatile memory
#406System and method for serial data communications between host and communications devices, and communications device employed in the system and method
#407Memory throughput increase via fine granularity of precharge management
#408MEMORY CARD AND METHOD OF WRITING DATA
#409Arrangements for Operating In-Line Memory Module Configurations
#410Direct memory access for advanced high speed bus
#411Reduction of latency in store and forward architectures utilizing multiple internal bus protocols
#412Mitigation of flash memory latency and bandwidth limitations via a write activity log and buffer
#413Memory buffering system that improves read/write performance and provides low latency for mobile systems
#414Selective preclusion of a bus access request
#415Memory hub with internal cache and/or memory access prediction
#416Managing write-to-read turnarounds in an early read after write memory system
#417Data processing system and method for memory arbitration
#418Memory with independent access and precharge
#419System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel
#420Detection of speculative precharge
#421Temperature throttling mechanism for DDR3 memory
#422MEMORY CONTROLLER AND PROCESSOR SYSTEM
#423High Performance and Endurance Non-volatile Memory Based Storage Systems
#424FRONT SIDE BUS PERFORMANCE USING AN EARLY DEFER-REPLY MECHANISM
#425Method and system for implementing generalized system stutter
#426Device Having a Low Latency Single Port Memory Unit and a Method for Writing Multiple Data Segments to a Single Port Memory Unit
#427High endurance non-volatile memory devices
#428Systems and methods for providing a dynamic memory bank page policy
#429Systems and methods for providing dynamic memory pre-fetch
#430Structure for multi-level memory architecture with data prioritization
#431Memory Command Issue Rate Controller
#432METHOD AND APPARATUS FOR REDUNDANT MEMORY ARRAYS
#433Memory hub and method for memory system performance monitoring
#434Method of memory management
#435Executing background writes to idle DIMMS
#436Memory controlling method
#437Resource management device
#438Dynamic verification traversal strategies
#439Detecting and resolving locks in a memory unit
#440Method and apparatus for conditional broadcast of barrier operations
#441Managing write-to-read turnarounds in an early read after write memory system
#442Method of Controlling A Memory Device Having a Memory Core
#443Bus system including a bus arbiter for arbitrating access requests
#444DRAM interface circuits that support fast deskew calibration and methods of operating same
#445Dynamic latency map for memory optimization
#446Multi-level memory architecture with data prioritization
#447Unified memory system
#448Memory interface with independent arbitration of precharge, activate, and read/write
#449Servicing commands
#450Memory system comprising a controller managing independent data transfer between input-output terminal, synchronous dynamic random access memory, and flash memory
#451High-speed controller for phase-change memory peripheral device
#452Dynamic update adaptive idle timer
#453Signal processor
#454Method, mobile device, system and software for flexible burst length control
#455Memory hub and method for memory system performance monitoring
#456Device for processing access concurrence to shared memory
#457Semiconductor integrated circuit and data processing system
#458Delayed memory access request arbitration
#459Memory hub with internal cache and/or memory access prediction
#460Memory controller and data processing system
#461Direct memory access for advanced high speed bus
#462Memory controller and memory control system predicting non-contiguous access
#463Executing background writes to idle DIMMs
#464Single burst completion of multiple writes at buffered DIMMs
#465Method and apparatus for managing write-to-read turnarounds in an early read after write memory system
#466Memory hub bypass circuit and method
#467System and method for interleaving SDRAM device access requests
#468Memory hub system and method having large virtual page size
#469Dynamic access scheduling memory controller
#470Methods and apparatus for servicing commands through a memory controller port
#471Memory control device
#472Method and apparatus for transmitting memory pre-fetch commands on a bus
#473Controller device and method for operating same
#474System and method for thermal throttling of memory modules
#475System and method for improving performance in computer memory systems supporting multiple memory access latencies
#476Memory controller with command queue look-ahead
#477Memory hub and access method having a sequencer and internal row caching
#478Flash memory system with a high-speed flash controller
#479System and method for organizing data transfers with memory hub memory modules
#480Resource management device
#481Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
#482Programmed access latency in mock multiport memory
#483Method and an apparatus for interleaving read data return in a packetized interconnect to memory
#484Memory system with parallel data transfer between host, buffer and flash memory
#485Method for controlling a memory access
#486Method and apparatus to manage memory access requests
#487Memory hub and method for memory system performance monitoring
#488Method and apparatus to counter mismatched burst lengths
#489Semiconductor device including a register to store a value that is representative of device type information
#490Arbitration of asynchronous and isochronous requests
#491Memory hub bypass circuit and method
#492Semiconductor integrated circuit and data processing system
#493Method and apparatus for sending data from multiple sources over a communications bus
#494Resource management during system verification
#495Automaton synchronization during system verification
#496Zero latency-zero bus turnaround synchronous flash memory
#497System verification using one or more automata
#498Method of controlling a memory device having a memory core
#499Memory arbiter with intelligent page gathering logic
#500Integrated circuit device
#501Memory module including an integrated circuit device
#502Arbitration sub-queues for a memory circuit
#503Flexible data handling
#504Selecting paths between a host and a storage system
#505Input/output (I/O) register reflected in CPU memory
#506System and method for device synchronization
#507Dynamic path selection in a storage network
#508Memory access quality-of-service reallocation
#509Low latency virtual general purpose input/output over I3C
#510Systems and methods for controlling data on a bus using latency
#511System and method for reducing read latency in storage devices
#512Method and apparatus for inter-die data transfer
#513Bandwidth-based path selection in a storage network
#514Scheduling memory requests with non-uniform latencies
#515Output data path for non-volatile memory
#516Cache management in a stream computing environment that uses a set of many-core hardware processors
#517Dynamically reconfiguring data plane of forwarding element to adjust data plane throughput based on detected conditions
#518Path selection in a data storage system
#519Memory utilization analysis for memory management systems
#520Buffered equidistant data acquisition for control applications
#521Data service-aware input/output scheduling
#522Low-skew channel bonding using oversampling
#523Read and write performance for non-volatile memory
#524Managing processing tasks in storage systems
#525Multi-input memory command prioritization
#526Multi-core device with multi-bank memory
#527Techniques for storage network bandwidth management
#528Policy based input/output dispatcher
#529Self-adaptive solid state drive controller
#530Integrated circuit and electric device for avoiding latency time caused by contention
#531Interface for ensuring efficient data requests