190322 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
Sub-classes:Distributed Management of Computer Express Link Fabric
#2MEMORY SYSTEM INCLUDING ADAPTABLE PHYSICAL CONNECTIVITY
#3Scalable System on a Chip
#4MEMORY SYSTEM WITH REGION-SPECIFIC MEMORY ACCESS SCHEDULING
#5METHODS AND APPARATUS FOR PSEUDO-SPLIT DIE MEMORY ACCESS
#6Balanced Latency Stacked Cache
#7BANK TO BANK DATA TRANSFER
#8COLD/HOT PHYSICAL PAGE IDENTIFICATION METHOD AND APPARATUS, CHIP, AND STORAGE MEDIUM
#9FEATURE DICTIONARY FOR BANDWIDTH ENHANCEMENT
#10Method and Apparatus for Collaborative Memory Accesses
#11KERNEL MAPPING TO NODES IN COMPUTE FABRIC
#12Clock Generation for Timing Communications with Ranks of Memory Devices
#13Predicting a load value for a subsequent load operation
#14DATA PROCESSING METHOD, COMPUTER DEVICE, AND READABLE STORAGE MEDIUM
#15Mechanism To Enhance PCIe Generation Switching
#16APPARATUS AND METHODS FOR REDUCING LATENCIES ASSOCIATED WITH LINK STATE TRANSITIONS WITHIN DIE INTERCONNECT ARCHITECTURES
#17DYNAMICALLY RECONFIGURING DATA PLANE OF FORWARDING ELEMENT TO ACCOUNT FOR POWER CONSUMPTION
#18PROCESSOR AND MEMORY COMMUNICATION IN A STACKED MEMORY SYSTEM
#19Scalable System on a Chip
#20TECHNIQUES FOR EFFICIENT PRE-FETCH DATA BUFFER MANAGEMENT BY A MEMORY CONTROLLER
#21STORAGE CONTROLLER AND STORAGE CONTROLLER CONTROL METHOD
#22Computer Architecture Having Selectable Parallel and Serial Communication Channels Between Processors and Memory
#23TECHNIQUES TO CONTROL SYSTEM UPDATES AND CONFIGURATION CHANGES VIA THE CLOUD
#24Scalable System on a Chip
#25A DATA PROCESSING APPARATUS AND METHOD FOR HANDLING STALLED DATA
#26STORAGE CONTROLLER MANAGING COMPLETION TIMING, AND OPERATING METHOD THEREOF
#27TECHNIQUES FOR DATA BUS INVERSION WITH IMPROVED LATENCY
#28MEMORY DEVICE WITH 4N AND 8N DIE STACKS
#29High bandwidth non-volatile memory for AI inference system
#30SEMICONDUCTOR DEVICE HAVING PDA FUNCTION
#31Streaming Transfers and Ordering Model
#32BANK TO BANK DATA TRANSFER
#33Bandwidth allocation
#34Technologies for dynamically managing resources in disaggregated accelerators
#35Artificial Reality System Having Multi-Bank, Multi-Port Distributed Shared Memory
#36JUST-IN-TIME (JIT) SCHEDULER FOR MEMORY SUBSYSTEMS
#37MEMORY APPARATUS FOR PROVIDING RELIABILITY, AVAILABILITY, AND SERVICEABILITY
#38Computer architecture having selectable parallel and serial communication channels between processors and memory
#39COMMAND ADDRESS INPUT BUFFER BIAS CURRENT REDUCTION
#40Dynamically reconfiguring data plane of forwarding element to account for power consumption
#41Clock generation for timing communications with ranks of memory devices
#42Kernel mapping to nodes in compute fabric
#43Quantum computing apparatus and associated methods
#44Application partitioning for locality in a stacked memory system
#45Streaming transfers and ordering model
#46MAXIMIZATION OF SPEEDS IN MIXED MEMORY MODULE CONFIGURATIONS
#47Peripheral component handling of memory read requests
#48Balancing Data Transfer Amongst Paths Between A Host and A Storage System
#49Techniques to control system updates and configuration changes via the cloud
#50Secure communication of virtual machine encrypted memory
#51PREFETCHER WITH LOW-LEVEL SOFTWARE CONFIGURABILITY
#52Accessing a memory using index offset information
#53Packet processing system, method and device utilizing a port client chain
#54Packet processing system, method and device utilizing a port client chain
#55Packet processing system, method and device utilizing a port client chain
#56Packet processing system, method and device utilizing a port client chain
#57MEMORY SYSTEM WITH REGION-SPECIFIC MEMORY ACCESS SCHEDULING
#58LOW LATENCY RETIMER AND LOW LATENCY CONTROL METHOD
#59Technologies for switching network traffic in a data center
#60Kernel mapping to nodes in compute fabric
#61Scalable system on a chip
#62Scalable system on a chip
#63Scalable system on a chip
#64Latency reduction in SPI flash memory devices
#65REDUCING LATENCY FOR MEMORY OPERATIONS IN A MEMORY CONTROLLER
#66Systems and methods to control bandwidth through shared transaction limits
#67SPECULATIVE HINT-TRIGGERED ACTIVATION OF PAGES IN MEMORY
#68Semiconductor device having PDA function
#69Artificial reality system having multi-bank, multi-port distributed shared memory
#70Method, apparatus, system for early page granular hints from a PCIe device
#71Bandwidth allocation for storage system commands in peer-to-peer environment
#72Technologies for dynamically managing resources in disaggregated accelerators
#73Feature dictionary for bandwidth enhancement
#74Memory request throttling to constrain memory bandwidth utilization
#75Storage controller managing completion timing, and operating method thereof
#76Storage device, operating method of storage device, and electronic device including storage device
#77Adapting Media Content to a Sensed State of a User
#78Just-in-time (JIT) scheduler for memory subsystems
#79Persisting directory onto remote storage nodes and smart downloader/uploader based on speed of peers
#80Reducing latency for memory operations in a memory controller
#81Techniques to configure physical compute resources for workloads via circuit switching
#82High throughput, low power, high parity architecture for database SSD
#83Industrial control system having multi-layered control logic execution
#84MEMORY POOLED TIME SENSITIVE NETWORKING BASED ARCHITECTURES
#85Technologies for switching network traffic in a data center
#86Dynamically reconfiguring data plane of forwarding element to account for power consumption
#87Memory sub-system including an in package sequencer separate from a controller
#88System and method for managing resources of a storage device and quantifying the cost of I/O requests
#89Priority scheduling in queues to access cache data in a memory sub-system
#90Packet processing system, method and device utilizing a port client chain
#91Systems and methods to control bandwidth through shared transaction limits
#92Technologies for dynamically managing resources in disaggregated accelerators
#93Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller
#94Systems and methods for sharing camera setting control among multiple image processing components in a vehicle
#95Control method of multiple memory devices and associated memory system
#96Active power management
#97Memory system with region-specific memory access scheduling
#98Storage controller managing completion timing, and operating method thereof
#99Semiconductor device having PDA function
#100Bank to bank data transfer
#101Systems and methods for adjusting one or more parameters of a GPU
#102Optimizing time-dependent simulations of quantum computing architectures
#103Techniques to support multiple interconnect protocols for a common set of interconnect connectors
#104Technologies for assigning workloads to balance multiple resource allocation objectives
#105Scheduling memory requests with non-uniform latencies
#106Low latency cache for non-volatile memory in a hybrid DIMM
#107Technologies for switching network traffic in a data center
#108Feature dictionary for bandwidth enhancement
#109Clock generation for timing communications with ranks of memory devices
#110Method of memory time division control and related device
#111Optimizing time-dependent simulations of quantum computing architectures
#112Speculative hint-triggered activation of pages in memory
#113ALUA/aggregated switch latency reduction system
#114Method and apparatus for performing dynamic throttling control with aid of configuration setting
#115High performance interconnect physical layer
#116MEMORY CONTROL COMPONENT WITH INTER-RANK SKEW TOLERANCE
#117Dynamically reconfiguring data plane of forwarding element to account for operating temperature
#118Bounded latency and command non service methods and apparatus
#119Variable read latency on a serial memory bus
#120Apparatus and methods for accelerating tasks during storage caching/tiering in a computing environment
#121Priority scheduling in queues to access cache data in a memory sub-system
#122Stale message removal in a multi-path lock facility
#123Memory systems and methods including training, data organizing, and/or shadowing
#124Memory controller for storage device, storage device, control method of storage device, and recording medium
#125Semiconductor device having PDA function
#126Orthogonal multi-phase scheduling circuitry
#127Data process execution device, storage medium, and data process execution system
#128Storing data from low latency storage
#129Apparatus and method for dynamically allocating data paths in response to resource usage in data processing system
#130Streaming platform flow and architecture for an integrated circuit
#131Queue depth management for host systems accessing a peripheral component interconnect express (PCIe) device via a PCIe switch
#132Bounded latency and command non service methods and apparatus
#133Beam scanning image processing within an improved graphics processor micro architecture
#134Interface for memory having a cache and multiple independent arrays
#135Interface scheduler for a distributed memory system
#136Memory sub-system including an in package sequencer separate from a controller
#137Unified address space for multiple hardware accelerators using dedicated low latency links
#138Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller
#139Scalable low-latency storage interface
#140System and method for performing per-bank memory refresh
#141Techniques to verify and authenticate resources in a data center computer environment
#142Method, system, and apparatus for reducing processor latency
#143System, apparatus and method for providing a local clock signal for a memory array
#144Memory system with latency distribution optimization and an operating method thereof
#145VARIABLE-STRIDE WRITE IN A MULTI-POINT BUS ARCHITECTURE
#146Cache management in a stream computing environment that uses a set of many-core hardware processors
#147Robotically serviceable computing rack and sleds
#148Method of signal integrity and power integrity analysis for address bus
#149Bank to bank data transfer
#150BURST-RESPONSIVE WIRELESS DOWNLOAD PACKET MANAGEMENT FOR REDUCING PROCESSING WORKLOAD LATENCY AND POWER CONSUMPTION
#151Method for sending by an upstream device to a downstream device data from a virtual channel sharing a same input buffer memory of the downstream device, corresponding computer program and system
#152Methods for parity error synchronization and memory devices and systems employing the same
#153Technologies for switching network traffic in a data center
#154Technologies for switching network traffic in a data center
#155Separating completion and data responses for higher read throughput and lower link utilization in a data processing network
#156Nucleic acid based data storage
#157Optimized locking for replication solutions
#158Variable read latency on a serial memory bus
#159Interface for memory having a cache and multiple independent arrays
#160Managing internal command queues in solid state storage drives
#161Memory controllers, memory systems, solid state drives and methods for processing a number of commands
#162MEMORY CONTROLLER AND OPERATING METHOD THEREOF
#163Adapting media content to a sensed state of a user
#164Packet processing system, method and device utilizing a port client chain
#165Aggregation handling
#166Providing multiple low power link state wake-up options
#167Clock generation for timing communications with ranks of memory devices
#168Method, system, and apparatus for reducing processor latency
#169Technologies for adaptive processing of multiple buffers
#170Memory component with multiple command/address sampling modes
#171High speed memory interface
#172Asynchronous buffer with pointer offsets
#173Memory request throttling to constrain memory bandwidth utilization
#174Clock line driving for single-cycle data over clock signaling and pre-emption request in a multi-drop bus
#175Speculative hint-triggered activation of pages in memory
#176Pipelined latches to prevent metastability
#177Memory system and operating method thereof
#178Method, apparatus, system for early page granular hints from a PCIe device
#179Cache management in a stream computing environment that uses a set of many-core hardware processors
#180Method and design for dynamic management of descriptors for SGL operation
#181SELECTING STORAGE UNITS OF A DISPERSED STORAGE NETWORK
#182Techniques for command arbitation in symmetric multiprocessor systems
#183Cache utilization of backing storage for aggregate bandwidth
#184Scalable memory-optimized hardware for matrix-solve
#185Computer architecture having selectable, parallel and serial communication channels between processors and memory
#186STORAGE DEVICE THAT STORES LATENCY INFORMATION, PROCESSOR AND COMPUTING SYSTEM
#187Technologies for optical communication in rack clusters
#188Technologies for switching network traffic in a data center
#189Apparatuses and methods for memory operations having variable latencies
#190Queue depth management for host systems accessing a peripheral component interconnect express (PCIe) device via a PCIe switch
#191Semiconductor device having PDA function
#192Timing esimation method and simulator
#193System and method for allocating memory devices among information handling systems in a chassis
#194Apparatuses and methods for variable latency memory operations
#195Iterative write sequence interrupt
#196Event-driven schemes for determining suspend/resume periods
#197Resilient vertical stacked chip network for routing memory requests to a plurality of memory dies
#198Scalable low-latency storage interface
#199System, apparatus and method for providing a local clock signal for a memory array
#200Beam scanning image processing within an improved graphics processor microarchitecture
#201NON-VOLATILE STORAGE DEVICE AND METHOD FOR ACCESSING NON-VOLATILE STORAGE DEVICE
#202Virtual channel and resource assignment
#203Controller reading data stored in a memory device using buffers, operating method thereof and memory system including controller
#204Scoreboard approach to managing idle page close timeout duration in memory
#205Memory system with latency distribution optimization and an operating method thereof
#206Managing data storage by an asynchronous copy service
#207Managing data storage by an asynchronous copy service
#208CACHE MANAGEMENT IN A STREAM COMPUTING ENVIRONMENT THAT USES A SET OF MANY-CORE HARDWARE PROCESSORS
#209CACHE MANAGEMENT IN A STREAM COMPUTING ENVIRONMENT THAT USES A SET OF MANY-CORE HARDWARE PROCESSORS
#210Cache management in a stream computing environment that uses a set of many-core hardware processors
#211Vehicle with improved I/O latency of ADAS system features operating on an OS hypervisor
#212Technologies for performing speculative decompression
#213High performance interconnect physical layer
#214Memory system including a plurality of memory devices having different latencies and operation method thereof
#215Systems and methods for low latency access of memory between computing devices
#216Low latency retimer
#217Efficient arbitration for memory accesses
#218Fabric independent PCIe cluster manager
#219Aggregation handling
#220Memory device with interleaved bank access
#221Memory control component with dynamic command/address signaling rate
#222System and method of determining memory access time
#223Nucleic acid based data storage
#224Automatic system service resource management for virtualizing low-latency workloads that are input/output intensive
#225PERFORMANCE RANKING OF READ REQUESTS IN A DISTRIBUTED STORAGE NETWORK
#226Controlling write pulse width to non-volatile memory based on free space of a storage
#227Dynamically determining memory attributes in processor-based systems
#228Technologies for cooling rack mounted sleds
#229Technologies for providing power to a rack
#230Robotically serviceable computing rack and sleds
#231Thermally efficient compute resource apparatuses and methods
#232Dynamic memory for compute resources in a data center
#233Disaggregated physical memory resources in a data center
#234Configurable computing resource physical location determination
#235Technologies for managing the efficiency of workload execution
#236Technologies for dynamically managing resources in disaggregated accelerators
#237Technologies for assigning workloads to balance multiple resource allocation objectives
#238Out-of-band management techniques for networking fabrics
#239Technologies for managing resource allocation with phase residency data
#240Techniques to configure physical compute resources for workloads via circuit switching
#241Technologies for allocating ephemeral data storage among managed nodes
#242Technologies for predictively managing heat generation in a datacenter
#243Technologies for dynamic remote resource allocation
#244Technologies for allocating resources within a self-managed node
#245Techniques to process packets in a dual-mode switching environment
#246Technologies for data center multi-zone cabling
#247Techniques to verify and authenticate resources in a data center computer environment
#248Techniques to support multiple interconnect protocols for a common set of interconnect connectors
#249Technologies for a low-latency interface to data storage
#250Technologies for dynamic allocation of tiers of disaggregated memory resources
#251Technologies for assigning workloads based on resource utilization phases
#252Technologies for performing partially synchronized writes
#253Storage sled and techniques for a data center
#254Accelerator resource allocation and pooling
#255Memory sharing for physical accelerator resources in a data center
#256Technologies for blind mating for sled-rack connections
#257Bank to bank data transfer
#258Method to handle host, device, and link's latency tolerant requirements over USB Type-C power delivery using vendor defined messaging for all alternate modes
#259Memory system and operation method of the same
#260Draining a write queue based on information from a read queue
#261Apparatuses and methods for memory operations having variable latencies
#262Apparatuses and methods for controlling wordlines and sense amplifiers
#263EMI mitigation on high-speed lanes using false stall
#264System and method of application aware efficient IO scheduler
#265Ring protocol for low latency interconnect switch
#266Data storage device and method thereof
#267Serial communication link with optimal transfer latency
#268Memory systems and methods including training, data organizing, and/or shadowing
#269Clock generation for timing communications with ranks of memory devices
#270FIXED LATENCY MEMORY CONTROLLER, ELECTRONIC APPARATUS AND CONTROL METHOD
#271OPTIMAL LATENCY PACKETIZER FINITE STATE MACHINE FOR MESSAGING AND INPUT/OUTPUT TRANSFER INTERFACES
#272Memory controller with interleaving and arbitration scheme
#273Packet processing system, method and device utilizing a port client chain
#274Intelligent coded memory architecture with enhanced access scheduler
#275Memory control component with inter-rank skew tolerance
#276Power gated communication controller
#277Memory device having bank interleaving access
#278High performance interconnect physical layer
#279MEMORY SYSTEM
#280Synchronous input/output using a low latency storage controller connection
#281Method and apparatus for preventing bank conflict in memory
#282STORAGE CONTROL DEVICE AND HIERARCHIZED STORAGE CONTROL METHOD
#283MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS
#284Fabric independent PCIe cluster manager
#285POWER GATED COMMUNICATION CONTROLLER
#286Memory interface system
#287NVM express controller for remote access of memory and I/O over Ethernet-type networks
#288LOW LATENCY MEMORY AND BUS FREQUENCY SCALING BASED UPON HARDWARE MONITORING
#289Memory subsystem and computer system
#290Memory subsystem and computer system
#291Memory system, memory module and method to backup and restore system using command address latency
#292Controller transmitting output commands and method of operating the same
#293Memory bus management
#294Packet processing system, method and device utilizing a port client chain
#295Performance-based grouping of storage devices in a storage system
#296Method and design for dynamic management of descriptors for SGL operation
#297Memory device with a control circuit to control data reads
#298Shaping I/O traffic by managing queue depth in fractional increments
#299Traffic rate control for inter-class data migration in a multiclass memory system
#300Coherent memory interleaving with uniform latency