190334 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Handling requests for interconnection or transfer for access to memory bus; Details of memory controller using buffers
Migrating buffer for direct memory access in a computer system
#1502Semiconductor device including a global buffer shared by a plurality of memory controllers
#1503COMPUTER HAVING BUFFERING CIRCUIT FOR HARD DISK DRIVE
#1504Electronic device and method for fabricating the same
#1505Multicasting computer bus switch
#1506Distributed interrupt scheme in a multi-processor system
#1507Managing buffered communication between cores
#1508Managing buffered communication between sockets
#1509Multi-channel IS transmit control system and method
#1510Method, apparatus, and system for speculative abort control mechanisms
#1511Method, apparatus, and system for speculative abort control mechanisms
#1512Method, apparatus, and system for speculative abort control mechanisms
#1513Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution
#1514Systems and methods for support of non-volatile memory on a DDR memory channel
#1515Methods and circuits for deadlock avoidance
#1516Asynchronous FIFO buffer with Johnson code write pointer
#1517Electronic device and method for fabricating the same
#1518Data transmitter apparatus and method for data communication using the same
#1519SYSTEM AND METHODS FOR PROCESSOR-BASED MEMORY SCHEDULING
#1520Frameless telecommunications enclosure
#1521Memory aggregation device
#1522Method and apparatus for message interactive processing
#1523System and method for improving memory transfer
#1524Read writeable randomly accessible non-volatile memory modules
#1525Memory access method, buffer scheduler and memory module
#1526Method and system for queuing data for multiple readers and writers
#1527Data transfer control apparatus
#1528Electronic device including memory cells having variable resistance characteristics
#1529Reducing latency in an expanded memory system
#1530Memory device having a tunnel barrier layer in a memory cell, and electronic device including the same
#1531Resource allocation by virtual channel management and bus multiplexing
#1532USB RAM device with buffer descriptor table and dynamically configurable endpoint allocation
#1533Command processing apparatus, method and integrated circuit apparatus
#1534Autonomous sleep mode
#1535Memory controller and method for controlling a memory device to process access requests issued by at least one master device
#1536Electric device having wire contacts coupled to stack structures with variable resistance elements
#1537Memory storage device and control method thereof and memory control circuit unit and module
#1538Atomic non-volatile memory data transfer
#1539Bus controller, data forwarding system, and method for controlling buses
#1540Optimized credit return mechanism for packet sends
#1541Solid state driving including nonvolatile memory, random access memory and memory controller
#1542Method and apparatus for cache memory data processing
#1543Method and apparatus for cache memory data processing
#1544Method and apparatus for handling incoming data frames
#1545Translation layer for controlling bus access
#1546High-speed memory system
#1547System and method for efficient processing of queued read commands in a memory system
#1548High speed flash controllers
#1549Remapping in a memory device
#1550Tracking a relative arrival order of events being stored in multiple queues using a counter
#1551Adaptive scheduling queue control for memory controllers based upon page hit distance determinations
#1552Service and system supporting coherent data access on multicore controller
#1553Network interface card rate limiting
#1554FIFO buffer clean-up
#1555Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device
#1556Communication via a memory interface
#1557Graphics processing microprocessor system having a master device communicate with a slave device
#1558Configurable peripheral componenent interconnect express (PCIe) controller
#1559Method and device for buffer processing in system on chip
#1560Memory control unit and data storage device including the same
#1561Dynamic temporary use of packet memory as resource memory
#1562Hazard checking control within interconnect circuitry
#1563Serial bus interface to enable high-performance and energy-efficient data logging
#1564Broadcast and unicast communication between non-coherent processors using coherent address operations
#1565Broadcast and unicast communication between non-coherent processors using coherent address operations
#1566Configurable buffer allocation for multi-format video processing
#1567Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system
#1568Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system
#1569Scalable, parameterizable, and script-generatable buffer manager architecture
#1570System and method for adaptive compression mode selection for buffers in a portable computing device
#1571Clock control for DMA busses
#1572System and method for despreader memory management
#1573System and method for computer memory with linked paths
#1574System and method for computer memory with linked paths
#1575Configurable read-modify-write engine and method for operating the same in a solid state drive
#1576Memory buffer with one or more auxiliary interfaces
#1577Software Enabled Network Storage Accelerator (SENSA) - Embedded Buffer for Internal Data Transactions
#1578System on chip and method of operating a system on chip
#1579METHOD AND APPARATUS USING HIGH-EFFICIENCY ATOMIC OPERATIONS
#1580System interconnect and operating method of system interconnect
#1581Arbitration circuit and processing method of arbitration circuit
#1582Efficient buffering for a system having non-volatile memory
#1583Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system
#1584Column bus driving method for micro display device
#1585Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system
#1586Semiconductor memory systems with on-die data buffering
#1587NETWORK INTERCONNECT WITH REDUCED CONGESTION
#1588Method and apparatus for DRAM spatial coalescing within a single channel
#1589Bus control device, relay device, and bus system
#1590Electronic device including a switch element in which a metal nitride layer has a nitrogen concentration increasing as a closer distance from a switching layer, and method for fabricating the same
#1591Lookahead scheme for prioritized reads
#1592Aligning FIFO pointers in a data communications lane of a serial link
#1593Resource allocation by virtual channel management and bus multiplexing
#1594COMMAND SCHEDULER FOR A DISPLAY DEVICE
#1595Opportunistic block transmission with time constraints
#1596High capacity memory system using standard controller component
#1597Nonvolatile memory system and operating method thereof
#1598Reduced host data command processing
#1599High capacity memory system using standard controller component
#1600Semiconductor device and memory system including the same
#1601Arithmetic processing unit, and method of controlling arithmetic processing unit
#1602Method for controlling multiple CAN interfaces through single SPI bus
#1603Electronic device
#1604Cache line eviction based on write count
#1605System and method for data synchronization across digital device interfaces
#1606Data write control device and data storage device
#1607Apparatuses and methods for providing data to a configurable storage area
#1608Method and system for buffer state based low power operation in a MoCA network
#1609Communication apparatus and data processing method
#1610Method of managing a solid state drive, associated systems and implementations
#1611System and method for increased capacity and scalability of a memory topology
#1612Dual asynchronous and synchronous memory system
#1613Command executing method, connector and memory storage device
#1614Message-based memory access apparatus and access method thereof
#1615Bridge circuit to arbitrate bus commands
#1616Method and apparatus for controlling memory operation
#1617Control device and access system utilizing the same
#1618Data processing device, semiconductor external view inspection device, and data volume increase alleviation method
#1619Asynchronous communication between devices
#1620Memory system with improved efficiency of data transfer between host, buffer, and nonvolatile memory
#1621Data-processing apparatus and data transfer control device
#1622System and method for storing and forwarding data from a vital-signs monitor
#1623Systems and methods for voice data processing
#1624Memory system, semiconductor memory device and operating method thereof
#1625Method and apparatus for writing data to a flash memory
#1626Semiconductor device for performing test and repair operations
#1627Reconfigurable load-reduced memory buffer
#1628Multilevel memory bus system
#1629Memory devices and systems including multi-speed access of memory modules
#1630Method and system for simplified address translation support for static infiniband host channel adaptor structures
#1631Asynchronous data mirroring in memory controller
#1632Mitigate flash write latency and bandwidth limitation by preferentially storing frequently written sectors in cache memory during a databurst
#1633System and method for providing a command buffer in a memory system
#1634Folded memory modules
#1635Requests and data handling in a bus architecture
#1636Architecture for writing and reading data in a data storage system
#1637Memory buffering system that improves read/write performance and provides low latency for mobile systems
#1638Dram compression scheme to reduce power consumption in motion compensation and display refresh
#1639Integrated circuit device and method for providing data access control
#1640Apparatus and method for memory-hierarchy aware producer-consumer instruction
#1641Merging eviction and fill buffers for cache line transactions
#1642Method to integrate ARM ecosystem IPs into PCI-based interconnect
#1643Systems and methods for support of non-volatile memory on a DDR memory channel
#1644Systems and methods for maintaining an order of read and write transactions in a computing system
#1645Tracking a relative arrival order of events being stored in multiple queues using a counter
#1646Tracking a relative arrival order of events being stored in multiple queues using a counter
#1647Memory controller and memory system including the same
#1648Contention blocking buffer
#1649System and method for providing a flash memory cache input/output throttling mechanism based upon temperature parameters for promoting improved flash life
#1650Method and system for performing data transfer with a flash storage medium
#1651Distributed data return buffer for coherence system with speculative address support
#1652Microcontroller input/output connector state retention in low-power modes
#1653Method and apparatus for turbo decoder memory collision resolution
#1654Memory operation upon failure of one of two paired memory devices
#1655Host device and system including the same
#1656Opportunistic block transmission with time constraints
#1657Efficient calibration of a low power parallel data communications channel
#1658Memory access system
#1659Configurable buffer allocation for multi-format video processing
#1660Memory controller devices, systems and methods for translating memory requests between first and second formats for high reliability memory devices
#1661Efficient memory management for parallel synchronous computing systems
#1662Memory sharing circuit employing a buffered address and data bus and preventing bus collision
#1663System and apparatus for flash memory data management
#1664Remapping and compacting in a memory device
#1665MEMORY CONTROLLER AND A METHOD THEREOF
#1666Method for managing buffer memory, memory controllor, and memory storage device
#1667Buffer managing method and buffer controller thereof
#1668Memory controller and memory access system with error detection using data comparison of loop-backed signals
#1669Memory interface circuit and semiconductor device
#1670Method and system for buffer state based low power operation in a MoCA network
#1671Methods and systems for routing in a state machine
#1672Memory controller and memory control method
#1673Memory bandwidth reallocation for isochronous traffic
#1674Drift detection in timing signal forwarded from memory controller to memory device
#1675Lookahead scheme for prioritized reads
#1676Graphics processing microprocessor system having a master device communicate with a slave device
#1677RAM memory device capable of simultaneously accepting multiple accesses
#1678ACCESS CONTROL APPARATUS, IMAGE FORMING APPARATUS, AND ACCESS CONTROL METHOD
#1679System on chip, electronic system including the same, and method of operating the same
#1680Storing data in any of a plurality of buffers in a memory controller
#1681MEMORY SYSTEM, MEMORY DEVICE AND MEMORY INTERFACE DEVICE
#1682Computing module with serial data connectivity
#1683Method for allocating addresses to data buffers in distributed buffer chipset
#1684Memory signal buffers and modules supporting variable access granularity
#1685Memory interface circuit and semiconductor device
#1686Partial-writes to ECC (error check code) enabled memories
#1687Requests and data handling in a bus architecture
#1688SEMICONDUCTOR STORAGE SYSTEM
#1689CPU connection circuit, data processing apparatus, arithmetic processing device, portable communication terminal using these modules and data transfer
#1690MEMORY CONTROLLER WITH BI-DIRECTIONAL BUFFER FOR ACHIEVING HIGH SPEED CAPABILITY AND RELATED METHOD THEREOF
#1691Configurable buffer allocation for multi-format video processing
#1692Mitigate flash write latency and bandwidth limitation with a sector-based write activity log
#1693Nonvolatile memory, memory controller, nonvolatile memory accessing method, and program
#1694DATA MANAGEMENT METHOD, DEVICE, AND DATA CHIP
#1695Data processing circuit with multiplexed memory
#1696Transmission control device, memory control device, and PLC including the transmission control device
#1697Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
#1698Memory system and method having volatile and non-volatile memory devices at same hierarchical level
#1699OPPORTUNISTIC BLOCK TRANSMISSION WITH TIME CONSTRAINTS
#1700Enforcing system intentions during memory scheduling
#1701Memory buffer for buffer-on-board applications
#1702Memory buffer for buffer-on-board applications
#1703Dynamic random access memory for a semiconductor storage device-based system
#1704Storage device with buffer memory including non-volatile RAM and volatile RAM
#1705METHOD AND APPARATUS FOR MEMORY CONTROL
#1706METHOD AND SYSTEM FOR RESOLVING INTEROPERABILITY OF MULTIPLE TYPES OF DUAL IN-LINE MEMORY MODULES
#1707METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING
#1708Control method and controller for DRAM
#1709Integrated circuit and method for reducing violations of a timing constraint
#1710Semiconductor memory device and method of controlling the same
#1711Opportunistic block transmission with time constraints
#1712EFFICIENT BUFFERING FOR A SYSTEM HAVING NON-VOLATILE MEMORY
#1713Interpreting I/O operation requests from pageable guests without host intervention
#1714MEMORY ACCESS APPARATUS AND DISPLAY USING THE SAME
#1715System and apparatus for flash memory data management
#1716Preparation of memory device for access using memory access type indicator signal
#1717Method for extracting IBIS simulation model
#1718One-way bus bridge
#1719Memory System
#1720Interface system, and corresponding integrated circuit and method
#1721Memory system and data transfer method
#1722Providing frame start indication in a memory system having indeterminate read data latency
#1723Providing frame start indication in a memory system having indeterminate read data latency
#1724Data storage apparatus with nonvolatile memories and method for controlling nonvolatile memories
#1725Multiple critical word bypassing in a memory controller
#1726Memory controller with emulative internal memory buffer
#1727Memory interface circuit and semiconductor device
#1728Opportunistic block transmission with time constraints
#1729System for controlling memory accesses to memory modules having a memory hub architecture
#1730Data processing apparatus
#1731High-speed memory system
#1732ALLOCATION OF MEMORY BUFFERS BASED ON PREFERRED MEMORY PERFORMANCE
#1733Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation
#1734System and method for a hierarchical buffer system for a shared data bus
#1735Performing multiple write operations to a memory using a pending write queue/cache
#1736Transferring data between memories over a local bus
#1737System and method for storing and forwarding data from a vital-signs monitor
#1738Computing module with serial data connectivity
#1739METHOD AND APPARATUS FOR CONCURRENTLY READING A PLURALITY OF MEMORY DEVICES USING A SINGLE BUFFER
#1740Nandflash controller and data transmission method with Nandflash controller
#1741CPU connection circuit, data processing apparatus, arithmetic processing device, portable communication terminal using these modules and data transfer method
#1742Method of managing a solid state drive, associated systems and implementations
#1743Method of managing a solid state drive, associated systems and implementations
#1744Requests and data handling in a bus architecture
#1745Memory controller, method of controlling unaligned memory access, and computing apparatus incorporating memory controller
#1746Semiconductor memory device and method of controlling the same
#1747Semiconductor memory device and method of controlling the same
#1748Memory card and memory controller
#1749Data storage device and method for handling data read out from memory using a ping-pong buffer
#1750Interpreting I/O operation requests from pageable guests without host intervention
#1751System and apparatus for enhancing data storage efficiency of a flash memory by reducing time for reorganizing data
#1752System for controlling memory accesses to memory modules having a memory hub architecture
#1753Memory system and method having volatile and non-volatile memory devices at same hierarchical level
#1754Multilevel memory bus system for solid-state mass storage
#1755Memory controller and associated control method
#1756Reconfigurable load-reduced memory buffer
#1757Command tag checking in a multi-initiator media controller architecture
#1758Direct memory access for loopback transfers in a media controller architecture
#1759Context execution in a media controller architecture
#1760Interrupt queuing in a media controller architecture
#1761Coalescing multiple contexts into a single data transfer in a media controller architecture
#1762Context processing for multiple active write commands in a media controller architecture
#1763DRAM control method and the DRAM controller utilizing the same
#1764Arbitrated access to memory shared by a processor and a data flow
#1765System, apparatus, and method for modifying the order of memory accesses
#1766Split transaction protocol for a bus system
#1767Memory having internal processors and data communication methods in memory
#1768Circuit providing load isolation and memory domain translation for memory module
#1769Information processor system
#1770Memory module
#1771Processor and data transfer method
#1772Apparatus and method for capturing serial input data
#1773Memory control device, data processor, and data read method
#1774Memory system and method having volatile and non-volatile memory devices at same hierarchical level
#1775Memory controller, system, and method for accessing semiconductor memory
#1776System and method for serial interface topologies
#1777Memory devices and systems including multi-speed access of memory modules
#1778Bit error rate reduction buffer, method and apparatus
#1779METHOD AND APPARATUS FOR ACCESSING MEMORY UNITS
#1780Memory access device outputting transfer request
#1781Memory controller including a dual-mode memory interconnect
#1782Data processing apparatus
#1783System and method for improving memory transfer
#1784STREAMING MEMORY CONTROLLER
#1785Method and system for controlling memory accesses to memory modules having a memory hub architecture
#1786Split transaction protocol for a bus system
#1787Memory system for selectively transmitting command and address signals
#1788System and method for high performance synchronous DRAM memory controller
#1789Apparatus and method for buffer management for a memory operating
#1790Computing module with serial data connectivity
#1791Architecture for data storage systems
#1792Method of managing a solid state drive, associated systems and implementations
#1793Request arbitration apparatus and request arbitration method
#1794Memory controller and memory control method
#1795Memory system with improved efficiency of data transfer between host, buffer, and nonvolatile memory
#1796FLASH MEMORY CONTROL APPARATUS HAVING SIGNAL-CONVERTING MODULE
#1797Device and method for scheduling transactions over a deep pipelined component
#1798Command processing apparatus, method and integrated circuit apparatus
#1799System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices
#1800Memory system and method having volatile and non-volatile memory devices at same hierarchical level