Conversion tool for moving from block-based persistence to byte-based persistence

Multi-mode memory module and memory component

Migrating buffer for direct memory access in a computer system

Memory device and memory system performing an unmapped read

Multi-queue device assignment for application groups

FIRST-IN-FIRST-OUT BUFFER

Method and system for managing host memory buffer of host using non-volatile memory express (NVME) controller in solid state storage device

Input/output (I/O) loopback function for I/O signaling testing

SEMICONDUCTOR MEMORY DEVICE

Power management

Technologies for providing FPGA infrastructure-as-a-service computing capabilities

Apparatus having direct memory access controller and method for accessing data in memory

Programmable memory transfer request processing units

Memory device and memory system including the same

READ WRITEABLE RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY MODULES

Apparatuses and methods for providing data to a configurable storage area

Flash storage failure rate reduction and hyperscale infrastructure robustness enhancement through the MRAM-NOR flash based cache architecture

Flow control in networking system-on-chip verification

Traffic shaping in networking system-on-chip verification

Latency test in networking system-on-chip verification

Bandwidth test in networking System-on-Chip verification

Storage apparatus accessed by using memory bus

System and method for routing bus including buffer

Back-pressure in virtual machine interface

Merged access units in frame buffer compression

Multiprocessor cache buffer management

METHOD AND DEVICE FOR STORING AN IMAGE INTO A MEMORY

Computing system with a nonvolatile storage and operating method thereof

Adjustments of buffer credits for optimizing the number of retry operations and transfer ready operations

Memory module, memory device, and processing device having a processor mode, and memory system

Data input/output unit, electronic apparatus, and control methods thereof

Data transition in highly parallel database management system

Randomized data distribution in highly parallel database management system

APPLICATION DIRECT ACCESS TO SATA DRIVE

Preserving deterministic early valid across a clock domain crossing

Memory module with timing-controlled data paths in distributed data buffers

Frame reception monitoring method in serial communications

Pre-transmission data reordering for a serial interface

Reconfigurable fabric direct memory access with multiple read or write elements

Cut-through buffer with variable frequencies

Receiving buffer credits by a plurality of channels of one or more host computational devices for transmitting data to a control unit

Data transfer device and data transfer method having a shorter time interval between pieces of final transfer data in a frame image

Memory modules and systems with variable-width data ranks and configurable data-rank timing

Ring buffer including a preload buffer

Data item order restoration

First-in-first-out buffer

System and method for dynamically allocating memory to hold pending write requests

Data transfer device and data transfer method for smoothing data to a common bus

Image processing device and image processing method

Systems and methods for implementing a user mode virtual serial communications port emulator

Maintaining ordering requirements while converting protocols in a communications fabric

SHARED BUFFERED MEMORY ROUTING

Controller and operating method thereof

Method for processing vehicle-to-X messages

Nondeterministic memory access requests to non-volatile memory

Dynamically determining memory attributes in processor-based systems

Communication between dataflow processing units and memories

IMPROVEMENT IN SENDING OF MULTIMEDIA STREAMS

Low power data transfer for memory subsystem using data pattern checker to determine when to suppress transfers based on specific patterns

Self-ordering buffer

Sending and receiving data between processing units

Buffer device, an electronic system, and a method for operating a buffer device

USB enabled base station for a headset

Electronic device and method for fabricating the same

Optimized credit return mechanism for packet sends

Memory circuit with integrated processor

Memory device, memory module, and memory system

System for managing memory devices

Opportunistic block transmission with time constraints

Method of achieving low write latency in a data storage system

Bad column management with data shuffle in pipeline

Memory system and operating method thereof

Data processing systems and a plurality of memory modules

Electronic device and method for fabricating the same

Memory controller arbiter with streak and read/write transaction management

Hybrid LPDDR4-DRAM with cached NVM and flash-nand in multi-chip packages for mobile devices

Interface apparatus and method

Method, apparatus and system for dynamic optimization of signal integrity on a bus

Direct memory access (DMA) unit with address alignment

Load reduced nonvolatile memory interface

Memory controller, memory buffer chip and memory system

Memory with alternative command interfaces

Systems and devices for accessing a state machine

Storage system and method for burst mode management using transfer RAM

Apparatus for controlling access to a memory device, and a method of performing a maintenance operation within such an apparatus

Display apparatus, signal transmitter, and data transmitting method for display apparatus

Transferring data between memory system and buffer of a master device

Scalable, parameterizable, and script-generatable buffer manager architecture

Coherent controller

System and method for operating a DRR-compatible asynchronous memory module

Memory and method for operating a memory with interruptible command sequence

Semiconductor device

High Performance, High Capacity Memory Systems and Modules

Memory systems, modules, and methods for improved capacity

High capacity memory system using controller component

Logical memory buffers for a media controller

Meter and method for determining meter readings and method for the wireless transmission of electrical energy

Switching device using buffering

SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS (DMA) OPERATIONS

Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system

DATA TRANSFER CONTROL SYSTEM, DATA TRANSFER CONTROL METHOD, AND PROGRAM STORAGE MEDIUM

Storage system and method for controlling command transmission

Onboard Kahn network type system comprising a plurality of source and destination actors in order to manage buffer memories based on tokens

Buffer mapping scheme involving pre-allocation of memory

Methods and systems for processing PRP/SGL entries

Apparatuses and methods for providing data to a configurable storage area

Apparatuses, systems, and methods for accurately measuring packet propagation delays through USB retimers

Sensor bus communication system

Efficient buffering for a system having non-volatile memory

Processing system with interspersed processors with multi-layer interconnection

Storage device

Semiconductor device including a request issuing controller

Dynamic altering of SRIOV virtual function (VF) resources including DMA windows without bringing down the VF

Reconfigurable data interface unit for compute systems

METHOD, APPARATUS, SYSTEM FOR INCLUDING INTERRUPT FUNCTIONALITY IN SENSOR INTERCONNECTS

System-on-chip and method for exchanging data between computation nodes of such a system-on-chip

Asynchronous communication protocol compatible with synchronous DDR protocol

Memory expansion apparatus includes CPU-side protocol processor connected through parallel interface to memory-side protocol processor connected through serial link

Power saving techniques for memory systems by consolidating data in data lanes of a memory bus

SPLIT TRANSACTION PROTOCOL FOR A BUS SYSTEM

HYBRID BUFFER MANAGEMENT SCHEME FOR IMMUTABLE PAGES

Bus bridge for translating requests between a module bus and an axi bus

Memory module threading with staggered data transfers

Adaptive buffering of data received from a sensor

DATA TRANSFER FOR MULTI-LOADED SOURCE SYNCHROUS SIGNAL GROUPS

Architectures and methods for processing data in parallel using offload processing modules insertable into servers

Optimized credit return mechanism for packet sends

Method, apparatus, communication equipment and storage media for determining link delay

Access control method, bus system, and semiconductor device

Data storage device and method thereof

SYSTEM-ON-CHIP FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING

METHOD AND APPARATUS FOR PROVIDING SMALL FORM-FACTOR PLUGGABLE (“SFP”) NON-VOLATILE MEMORY (“NVM”) STORAGE DEVICES

Extended selection and alignment of video segments for adaptive streaming

Universal SPI (Serial Peripheral Interface)

Inline cryptographic engine (ICE) for peripheral component interconnect express (PCIe) systems

Systems and methods of secure domain isolation involving separation kernel features

Peripheral bus video communication using internet protocol

Method for reduced load memory module

Asymmetrical emphasis in a memory data bus driver

Scalable input/output system and techniques to transmit data between domains without a central processor

Performing caching utilizing dispersed system buffers

Generating a transition signal for controlling memory data output

Storage Device With Power Management Throttling

System and method for protecting plain text scripting language programs in a mainframe rehosting platform

Using dynamic bursts to support frequency-agile memory interfaces

Techniques to access or operate a dual in-line memory module via multiple data channels

Memory apparatus including multiple buffers and method of driving memory including multiple buffers

Electronic device and method for fabricating the same

Multi-core communication acceleration using hardware queue device

Electronic device and method for fabricating the same

System and method for preventing time out in input/output systems

Semiconductor device including a plurality of circuits and a bus connecting the circuits to one another, and method of operating the semiconductor device

Arbitration of requests requiring a variable number of resources

Peripheral interface circuit

Network interface card rate limiting

System and method for efficient cross-controller request handling in active/active storage systems

Reconfigurable interconnected programmable processors

Sending packets using optimized PIO write sequences without SFENCES

Electronic device and method of driving the same

Centrally managed unified shared virtual address space

Drift detection in timing signal forwarded from memory controller to memory device

Component carrier with converter board

Memory package including buffer, expansion memory module, and multi-module memory system

Memory devices and methods having instruction acknowledgement

Packet processing system, method and device utilizing a port client chain

Electronic system with memory management mechanism and method of operation thereof

Electronic device

Streaming engine with deferred exception reporting

DIRECT MEMORY ACCESS SYSTEM USING AVAILABLE DESCRIPTOR MECHANISM AND/OR PRE-FETCH MECHANISM AND ASSOCIATED DIRECT MEMORY ACCESS METHOD

Direct interface between graphics processing unit and data storage unit

Memory module with timing-controlled data paths in distributed data buffers

Programmable input/output (PIO) engine interface architecture with direct memory access (DMA) for multi-tagging scheme for storage devices

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME

System and method for dynamically adjusting a recording bitrate to accommodate a writing speed of a storage device

Delta-Sigma ADC with wait-for-sync feature

Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device

Nonvolatile memory device for providing fast booting and system including the same

System, device and method for transmitting signals between different communication interfaces

Modular ultra-wide internal bus mainframe processing units

Buffering request data for in-memory cache

Data output dispatching device and method

High performance interconnect physical layer

Implied directory state updates

MEMORY SYSTEM

Memory system

DEVICE, SYSTEM AND METHOD FOR LOW SPEED COMMUNICATION OF SENSOR INFORMATION

Semiconductor device

Bus for communication between devices

Semiconductor memory systems with on-die data buffering

Memory module with reduced read/write turnaround overhead

Low-layer memory for a computing platform

Fault tolerant memory systems and components with interconnected and redundant data interfaces

INTEGRATED CIRCUIT WITH LOW LATENCY AND HIGH DENSITY ROUTING BETWEEN A MEMORY CONTROLLER DIGITAL CORE AND I/OS

System and method for controlling memory frequency using feed-forward compression statistics

Memory system that selects data to be transmitted from a data buffer through a port

Data storage device and data reading method thereof

Microcontroller input/output connector state retention in low-power modes

COMPUTING MODULE WITH SERIAL DATA CONNECTIVITY

Storage device including random access memory devices and nonvolatile memory devices

Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines

SEMICONDUCTOR SYSTEM AND CONTROLLING METHOD THEREOF

Device including a single wire interface and a data processing system having the same

Per-DRAM and per-buffer addressability shadow registers and write-back functionality

Apparatuses and methods for transferring data from memory on a data path

Semiconductor memory device and memory system

Antenna buffer management for downlink physical layer

ASYNCHRONOUS FIRST-IN FIRST-OUT BUFFER APPARATUS WITH ACTIVE RATE CONTROL AND DYNAMIC RATE COMPENSATION AND ASSOCIATED NETWORK DEVICE USING THE SAME

High speed flash controllers

HYBRID COMPUTING MODULE

Hybrid computing module

Hybrid computing module

Hybrid computing module

Method and system for flexible credit exchange within high performance fabrics

Folded memory modules

Method and System for USB 2.0 Bandwidth Reservation

Network unit of electronic appliances, network of electronic appliances, and method of using chip identification device

Memory having internal processors and data communication methods in memory

Electronic device and method for fabricating the same

MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS

SPI Interface With Less-Than-8-Bit Bytes And Variable Packet Size

Electronic device

USB SWITCH AND CONTROL METHOD THEREOF

Software-based ultrasound imaging system

Memory system having lower pages and upper pages performing status read operation and method of operating the same

Lock-free processing of stateless protocols over RDMA

Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system

Pattern-based service bus architecture using activity-oriented services

SYSTEM AND METHOD FOR OFFSETTING THE DATA BUFFER LATENCY OF A DEVICE IMPLEMENTING A JEDEC STANDARD DDR-4 LRDIMM CHIPSET

Electronic device

Method of managing data of storage devices responsive to temperature

I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator

Systems and methods involving data bus inversion memory circuitry, configuration(s) and/or operation

Memory system design using buffer(s) on a mother board

Reestablishing synchronization in a memory system

Storage device and operating method thereof

Information processing apparatus, method, and computer readable medium

ONE-WAY BUS BRIDGE

Receiving buffer credits by a plurality of channels of one or more host computational devices for transmitting data to a control unit

DATA MEMORY DEVICE

Information processing apparatus, memory controller, and memory control method

Apparatus for monitoring data access to internal memory device and internal memory device

Adjustments of buffer credits for optimizing the number of retry operations and transfer ready operations

Power management

Processing system with interspersed processors with multi-layer interconnection

Method and system for bidirectional communication

Processing system with interspersed processors DMA-FIFO

Electronic device, adapter device, and video data processing method thereof

Central processing unit with enhanced instruction set

Controlling data transfer for data processing

Method for monitoring the operation of a component

SECURE DIGITAL HOST CONTROLLER VIRTUALIZATION

High capacity memory system with improved command-address and chip-select signaling mode

Peripheral interface circuit for serial memory

Packet processing system, method and device to optimize packet buffer space

Memory system facilitating high bandwidth and high capacity memory

BUS SYSTEM INCLUDING BRIDGE CIRCUIT FOR CONNECTING INTERLOCK BUS AND SPLIT BUS

Packet processing system, method and device utilizing a port client chain

Control path subsystem, method and device utilizing memory sharing

Approach for chip-level flop insertion and verification based on logic interface definition

POWER REDUCTION IN BUS INTERCONNECTS

Electronic device and method for fabricating the same

Systems and methods for implementing a user mode virtual serial communications port emulator

Bus interface device that merges data request signals, semiconductor integrated circuit device including the same, and method of operating the same

Microprocessor systems

Shared buffered memory routing

System and method for providing keyboard, video, and mouse functionality

WEAKLY ORDERED DOORBELL

Low-pin microcontroller device with multiple independent microcontrollers

Low-pin microcontroller device with multiple independent microcontrollers

Semiconductor storage device

Buffer management method and apparatus for universal serial bus communication in wireless environment

Circuits and methods for inter-processor communication

Module based data transfer

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

Line-multiplexed UART

Efficient calibration of a low power parallel data communications channel

Methods and systems for routing in a state machine

Memory buffer with one or more auxiliary interfaces

Configurable serial and pulse width modulation interface

Set buffer state instruction

Unified Memory Bus and Method to Operate the Unified Memory Bus

EMBEDDED RESILIENT BUFFER

12C bus controller slave address register and command FIFO buffer

Interrupt-driven I/O arbiter for a microcomputer system

Multiprocessor cache buffer management

Buffer device, method and apparatus for controlling access to internal memory

Bus access controller, hardware engine, controller, and memory system

Apparatus and method for buffered interconnect

MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME

Hardware accelerator and chip

Opportunistic block transmission with time constraints

High capacity memory system using standard controller component

Reordering responses in a high performance on-chip network

Packed write completions

Electronic device including fuse element having three or more junctions for reduced area and improved degree of integration

Physical interface for a serial interconnect

Semiconductor devices and semiconductor systems including the same

Display controller and a method thereof

Memory with alternative command interfaces

Migrating buffer for direct memory access in a computer system