Buffer Optimization for Reconfigurable Computing Environments

Communications to Dynamic Allocate a Host Memory Buffer

SINGLE-WRITER B-TREE ARCHITECTURE ON DISAGGREGATED MEMORY

HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE

BUFFER COMMUNICATION FOR DATA BUFFERS SUPPORTING MULTIPLE PSEUDO CHANNELS

MEMORY BUFFERS

DYNAMIC PRIORITY INVERSION FOR HOST MEMORY BUFFER HANDLING BASED ON A SYSTEM STATE

APPARATUSES, SYSTEMS, AND METHODS FOR STORING AND ACCESSING MEMORY METADATA AND ERROR CORRECTION CODE DATA

SYSTEMS AND METHODS FOR SEMICONDUCTOR DEVICES WITH EXTENDED HIGH-BANDWIDTH MEMORY (HBM) OFFSETS

MEMORY CONTROLLER FOR PROCESSING IN MEMORY AND MEMORY GENERATION METHOD USING MEMORY CONTROLLER

ENHANCED PERIPHERAL PROCESSING SYSTEM TO OPTIMIZE POWER CONSUMPTION

METHOD OF SHARING MEMORY CROSS OPERATING SYSTEMS, APPARATUS, CIRCUIT, MEDIUM, AND DEVICE

METHOD FOR PERFORMING ACCESS CONTROL OF MEMORY DEVICE WITH AID OF EXPANDER ARCHITECTURE, AND ASSOCIATED APPARATUS

PERIPHERAL COMPONENT INTERCONNECT EXPRESS BUS UNIT (PBU)-TO-NEST DIRECTED OPERATIONS

SCAN CONVERSION CIRCUIT AND METHOD OF CONVERTING DATA SCAN PATTERN

BUFFER MANAGEMENT IN FLASH MEMORY

COMMUNICATION DEVICE AND RECEPTION DATA PROCESSING METHOD IN COMMUNICATION DEVICE

REMOTE DIRECT MEMORY ACCESS BASED IMPLEMENTATION OF THE LOGICAL EXECUTION TIME PARADIGM

METHODS FOR DISTRIBUTING SOFTWARE-DETERMINED GLOBAL LOAD INFORMATION

TRACKING ACCESSES TO A MEMORY USING A RING-BUFFER STRUCTURE

APPARATUS WITH PARALLEL ARTIFICIAL INTELLIGENCE COMPUTATION CIRCUIT AND METHODS FOR OPERATING THE SAME

TECHNIQUES FOR INCREASING CAPACITY OF DRAM USING A COMMON DRAM DIE

STORAGE DEVICE

SYSTEMS, METHODS, AND DEVICES FOR NEAR DATA PROCESSING

Command Processing In Sequential Write Required Zone

WRITE BUFFER CIRCUIT SUPPORTING STORE RELEASE COMBINING OF STORE OPERATIONS FROM A MEMORY ACCESS STAGE OF A PROCESSOR INSTRUCTION PIPELINE FOR EFFICIENT PROCESSING OF STORE RELEASE INSTRUCTIONS, AND RELATED METHODS

AUDIO RECORDING METHOD WITH LOSS-MITIGATING BUFFER SYSTEM

COMBINING READ REQUESTS HAVING SPATIAL LOCALITY

ELECTRONIC DEVICE HAVING A PLURALITY OF CHIPLETS

HARDWARE STRUCTURES AND TECHNIQUES FOR REPLAYING PREFETCH VIRTUAL ADDRESSES

MEMORY PROCESSING METHOD, ELECTRONIC DEVICE, AND READABLE STORAGE MEDIUM

REAL-TIME DATA TRANSFER SCHEME FROM LIMITED POWER EMBEDDED SYSTEMS

Method and System for Optimizing Buffer Reservation and Utilization

COMPUTING SYSTEM CAPABLE OF DETECTING INTERLEAVING CONFIGURATION

Prefetch Memory Management Unit for Real-Time Virtual Memory Address Translation

STORAGE DEVICE, MEMORY CONTROLLER AND METHOD OF OPERATING MEMORY CONTROLLER

LOAD AND STORE MEMORY ARCHITECTURE

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

NVMe SSD AND STORAGE SYSTEM INCLUDING THE SAME

GENERATING A METADATA CACHE FOR A BACKUP

DELAYED MEMORY MANAGEMENT OPERATIONS

METHOD AND SYSTEM FOR FACILITATING WIDE LAG AND ECMP CONTROL

DYNAMIC BUFFER MANAGEMENT IN DATA-DRIVEN INTELLIGENT NETWORK

SYSTEM AND METHOD FOR FACILITATING DATA REQUEST MANAGEMENT IN A NETWORK INTERFACE CONTROLLER (NIC)

MEMORY ACCESS OPERATIONS BASED ON SCORES

Write Amplification Reduction with Sub-Indirection Unit (IU) Hinting

DISTRIBUTED HYBRID BUFFER FOR MEMORY SYSTEMS

DYNAMIC BYTE CONFIGURATION FOR COMPUTATIONAL PROGRAM INTERPRETATION

SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE FOR PERFORMING OPERATIONS

Chiplet Hub with Multi-Unit Accessible HBM

COMPOSABLE INFRASTRUCTURE ENABLED BY HETEROGENEOUS ARCHITECTURE, DELIVERED BY CXL BASED CACHED SWITCH SOC AND EXTENSIBLE VIA CXLOVERETHERNET (COE) PROTOCOLS

Z-Dimension Cache Layer Pipelining

WRITE MERGING ON STORES WITH DIFFERENT TAGS

SCALABLE INPUT/OUTPUT MEMORY MANAGEMENT UNIT (IOMMU) COMMAND PROCESSING

MEMORY DEVICE PERFORMING SELF-CALIBRATION BY IDENTIFYING LOCATION INFORMATION AND MEMORY MODULE INCLUDING THE SAME

SYSTEMS AND METHODS FOR TASK SWITCHING IN NEURAL NETWORK PROCESSOR

MEMORY SYSTEM AND CONTROL METHOD

MEMORY PROTOCOLS OVER OFF-PACKAGE INTERCONNECTS

Transaction Method and Transaction System Capable of Reducing Dynamic Random-Access Memory Traffic

MEMORY MANAGEMENT METHOD AND APPARATUS, MEDIUM, AND ELECTRONIC DEVICE

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME

UPDATING A WRITE-DONE POINTER IN A FIRST-IN-FIRST-OUT QUEUE ON A PARALLELIZED DEVICE

PERFORMING DISTRIBUTED JOINS USING COMPUTE EXPRESS LINK (CXL) IN DATABASE MANAGEMENT SYSTEMS

COALESCING OF DATA AT A STORAGE DEVICE CONTROLLER

SYSTEM AND METHOD FOR DYNAMIC ALLOCATION OF REDUCTION ENGINES

METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM

STORAGE DEVICE INCLUDING TEST STORAGE BLOCK AND COMPUTING SYSTEM

MEMORY CONTROLLER COMPRESSING AND STORING DATA, METHOD OF OPERATING THE SAME, AND STORAGE DEVICE INCLUDING THE SAME

STORAGE DEVICE, HOST DEVICE AND DATA TRANSFER METHOD THEREOF

CIRCULAR QUEUE MANAGEMENT WITH NONDESTRUCTIVE SPECULATIVE READS

Memory-Request Priority Up-Leveling

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A COHERENT VICTIM CACHE WITH PARALLEL DATA PATHS

MEMORY ACCESS DEVICE AND OPERATING METHOD THEREOF

System and Method to Efficiently Assist Time-Synchronous Media Streaming and Remote-Control Applications

BUFFERING ELEMENTS FOR PROCESSING

SYSTEM AND METHOD FOR FACILITATING DATA-DRIVEN INTELLIGENT NETWORK WITH INGRESS PORT INJECTION LIMITS

DATA PACKING FOR POWER AND AREA-EFFICIENT MEMORY STRUCTURES AND PERFORMANCE-EFFICIENT DECODING OF ENCODED DATA

METHODS AND APPARATUS TO ACCESS MAIN MEMORY

INTERFACE SYSTEM AND OPERATING METHOD THEREOF

SYSTEM AND METHOD FOR PRIMARY STORAGE WRITE TRAFFIC MANAGEMENT

TRACKING MEMORY DEFECTS USING A SHARED MEMORY DEFECT LIST

LOCAL NON-VOLATILE MEMORY EXPRESS VIRTUALIZATION DEVICE

STORAGE DEVICE, STORAGE SYSTEM AND OPERATING METHOD OF THE SAME USING MEMORY BUFFER

TOKEN-CONTROLLED STREAMING ORDERED WRITE IN DATA COMMUNICATION

WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

INTERFACE DEVICE HAVING PLURALITY OF PORTS AND METHOD OF OPERATING THE SAME

VICTIM CACHE WITH WRITE MISS MERGING

DYNAMIC ROUTING OF TEXTURE LOADS IN GRAPHICS PROCESSING

MEMORY CONTROLLERS AND STORAGE DEVICES INCLUDING THE SAME

DMA DEVICE, OPERATING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING DMA DEVICE

CONFIGURABLE TYPES OF WRITE OPERATIONS

MEMORY DEVICE

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

INTER-PROCESS DATA TRANSMISSION METHOD AND APPARATUS, ELECTRONIC DEVICE, AND STORAGE MEDIUM

MEMORY MODULE THREADING WITH STAGGERED DATA TRANSFERS

SYSTEM AND METHOD FOR PERFORMING ON-THE-FLY REDUCTION IN A NETWORK

MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY

SYSTEM AND METHOD FOR FACILITATING DATA-DRIVEN INTELLIGENT NETWORK WITH ENDPOINT CONGESTION DETECTION AND CONTROL

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

ELECTRONIC DEVICE HAVING A PLURALITY OF CHIPLETS

CHIPLET HAVING SAVE AND FORWARD MODULE

Memory Modules and Systems with Variable-Width Data Ranks and Configurable Data-Rank Timing

PUSH-PULL MECHANISMS FOR HANDLING DATAFLOW BETWEEN CIRCUIT BLOCKS

ELECTRONIC DEVICE HAVING A PLURALITY OF CHIPLETS

NVMe Completion And Interrupt

DYNAMICALLY SHAPING AND SEGMENTING WORK UNITS FOR PROCESSING IN NEURAL NETWORK PROCESSOR

LATENCY-DRIVEN SHARED BUFFER ALGORITHM

SYSTEMS AND DEVICES FOR ACCESSING A STATE MACHINE

Single-writer B-tree Architecture on Disaggregated Memory

STORAGE DEVICE SHARING METHOD AND APPARATUS, AND SYSTEM

USER MODE DIRECT DATA ACCESS TO NON-VOLATILE MEMORY EXPRESS DEVICE VIA KERNEL-MANAGED QUEUE PAIR

ASYMMETRIC-CHANNEL MEMORY SYSTEM

Peer-To-Peer Communication Using Drain Buffers In Multi-Function Device

MEMORY INTERFACE HAVING MULTIPLE SNOOP PROCESSORS

QUALITY OF SERVICE CONTROL FOR READ OPERATIONS IN MEMORY SYSTEMS

Ring Buffer Storage Method and Ring Buffer Storage System Capable of Minimizing Extra Overhead Utilization

PAGE DETECTION USING RECENCY SCORE FILTERS

INTER-DRIVE COMMUNICATION FOR COOPERATIVE OPERATIONS

CACHE EVICT DUPLICATION MANAGEMENT

PACKET ROUTING BETWEEN MEMORY DEVICES AND RELATED APPARATUSES, METHODS, AND MEMORY SYSTEMS

MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

Prefetch Memory Management Unit for Real-Time Virtual Memory Address Translation

STORAGE CONTROLLER, OPERATING METHOD OF THE STORAGE CONTROLLER, AND OPERATING METHOD OF STORAGE DEVICE

MULTI-DOMAIN STORAGE DEVICE PERFORMING DOMAIN BALANCING OPERATION AND OPERATION METHOD THEREOF

CONTROLLER COMMAND SCHEDULING IN A MEMORY SYSTEM TO INCREASE COMMAND BUS UTILIZATION

NON-VOLATILE MEMORY BASED NEAR-MEMORY COMPUTING MACHINE LEARNING ACCELERATOR

SYSTEM AND METHOD FOR FACILITATING DATA-DRIVEN INTELLIGENT NETWORK WITH PER-FLOW CREDIT-BASED FLOW CONTROL

SYSTEM AND METHOD FOR FACILITATING EFFICIENT PACKET FORWARDING IN A NETWORK INTERFACE CONTROLLER (NIC)

SYSTEMS AND METHODS FOR BUFFER MANAGEMENT DURING A DATABASE BACKUP

Non-Blocking Chipkill Recovery

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO

MEMORY CONTROLLER INCLUDING A WRITE STAGING BUFFER TO MANAGE WRITE REQUESTS IN A MEMORY DEVICE

DATA INTERACTION METHOD, APPARATUS AND SYSTEM, AND ELECTRONIC DEVICE AND STORAGE MEDIUM

SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE

FOLDED MEMORY MODULES

DEVICE AND METHODS FOR FUNCTIONAL DESCRIPTOR-BASED DMA CONTROLLER

Memory Controller Reservation of Retry Queue

MEMORY MODULE WITH MEMORY-OWNERSHIP EXCHANGE

Memory Controller Reservation of Resources for Cache Hit

DOUBLE-HELIX SCHEDULING METHOD FOR SOUNDCARD BUFFERS DURING SOUND RECORDING AND REPRODUCTION

MULTI-BANK MEMORY THAT SUPPORTS MULTIPLE READS AND MULTIPLE WRITES PER CYCLE

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRITE MERGING

HOST SYSTEM DIAGNOSTIC TESTING

HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT

SYSTEM POWER REDUCTION FOR DDR5 INFORMATION HANDLING SYSTEMS

NEURAL NETWORK ACCELERATOR WITH MEMORY HAVING BANK-SPECIFIC CLOCK DOMAIN CROSSING BUFFERS

ENCODING AND DECODING APPARATUSES AND METHODS FOR IMPLEMENTING MULTI-MODE CODING

Low Latency Offloading of Collectives over a Switch

FLASH MEMORY CONTROLLER, OPERATING METHOD OF FLASH MEMORY CONTROLLER, AND STORAGE DEVICE CAPABLE OF PERFORMING DIFFERENT DIMENSION ERROR CORRECTION TO PROTECT DATA

MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM

INITIALIZING MEMORY SYSTEMS

Interrupt Latency Resilient UART Driver

ACCELERATOR SYSTEM AND METHOD TO EXECUTE DEPTHWISE SEPARABLE CONVOLUTION

METHOD FOR COMMUNICATION BETWEEN COMPONENTS OF AN ELECTRICAL DEVICE

Computer Memory Expansion Device and Method of Operation

CONTEXT-BASED COMPRESSION IN A MEMORY SYSTEM

FLASH ARBITRATION IN HETEROGENEOUS COMPUTING PLATFORMS

Request processing method and apparatus, device, and medium

MEMORY SYSTEM CHANGING WRITE MODE AND METHOD OF CONTROLLING NONVOLATILE MEMORY BY CHANGING WRITE MODE

SYSTEM AND METHODS FOR COMPUTING PARITY INFORMATION IN A RAID ARRAY

ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR PROTOCOL

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED DATA RAM CACHE FOR BANK ARBITRATION

USING DYNAMIC BURSTS TO SUPPORT FREQUENCY-AGILE MEMORY INTERFACES

SYSTEM AND METHOD FOR FACILITATING EFFICIENT LOAD BALANCING IN A NETWORK INTERFACE CONTROLLER (NIC)

MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

AREA EFFICIENT ASYNCHRONOUS FIRST-IN-FIRST-OUT (FIFO) BUFFER FOR HIGH BANDWIDTH DATA TRANSFER USING EVENT TRANSFER BLOCKS

HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE

COMMAND SCHEDULING COMPONENT FOR MEMORY

STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING

SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE FOR MODE BASED OPERATIONS

Tracing for High Bandwidth Masters in SoC

SYSTEMS, METHODS, AND APPARATUS TO ENABLE DATA AGGREGATION AND ADAPTATION IN HARDWARE ACCELERATION SUBSYSTEMS

SYSTEMS AND METHODS FOR REDUCING LATENCY AND IMPROVING PERFORMANCE IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM

MEMORY DEVICE FOR WAFER-ON-WAFER FORMED MEMORY AND LOGIC

Direct memory access architecture, system and method, electronic device, and medium

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SYSTEM

PROCESSOR AND MEMORY COMMUNICATION IN A STACKED MEMORY SYSTEM

SYSTEMS, METHODS, AND APPARATUS FOR CACHE OPERATION IN STORAGE DEVICES

SYSTEMS AND METHODS FOR SEMICONDUCTOR DEVICES WITH EXTENDED HIGH-BANDWIDTH MEMORY (HBM) OFFSETS

PARALLEL DATA READ OUT FROM BUFFER IN BUS PROTOCOL ENVIRONMENT

TECHNIQUES FOR EFFICIENT PRE-FETCH DATA BUFFER MANAGEMENT BY A MEMORY CONTROLLER

Distributing Virtual Channel Requests with Multiple Memory Modules

MEMORY DEVICE, FLASH MEMORY CONTROLLER AND ASSOCIATED CONTROL METHOD

VIRTUAL PARTITIONING A PROCESSOR-IN-MEMORY ("PIM")

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY

MOBILE IOT EDGE DEVICE USING 3D-DIE STACKING RE-CONFIGURABLE PROCESSOR MODULE WITH 5G PROCESSOR-INDEPENDENT MODEM

MEMORY SYSTEMS AND OPERATING METHODS THEREOF

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME

SEMICONDUCTOR DEVICE

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A VICTIM CACHE

Memory controller which implements partial writes with error signaling

METHOD TO SELECT PHYS AND A CONFIGURATION OF THE DATA PATH IN A MULTI PHY DRAM

DRIFT DETECTION IN TIMING SIGNAL FORWARDED FROM MEMORY CONTROLLER TO MEMORY DEVICE

DEADLOCK-FREE MULTICAST ROUTING ON A DRAGONFLY NETWORK

PROCESSOR SYSTEM AND METHOD FOR INCREASING DATA-TRANSFER BANDWIDTH DURING EXECUTION OF A SCHEDULED PARALLEL PROCESS

Duplicated Registers in Chiplet Processing Units

HANDSHAKING METHOD AND DATA STORAGE SYSTEM

METHOD AND SYSTEM FOR PROVIDING NETWORK INGRESS FAIRNESS BETWEEN APPLICATIONS

WEIGHTING ROUTING

PAYLOAD STORE WITH RANDOMIZED DATA DISTRIBUTION BETWEEN A SET OF NODES AND METHODS FOR USE THEREWITH

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

APPARATUS AND METHOD FOR SUPPORTING DATA INPUT/OUTPUT OPERATION BASED ON A DATA ATTRIBUTE IN A SHARED MEMORY DEVICE OR A MEMORY EXPANDER

VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM

SYSTEM AND METHOD FOR FACILITATING TRACER PACKETS IN A DATA-DRIVEN INTELLIGENT NETWORK

SYSTEM AND METHOD FOR FACILITATING DATA-DRIVEN INTELLIGENT NETWORK WITH FLOW CONTROL OF INDIVIDUAL APPLICATIONS AND TRAFFIC FLOWS

COMBINING READ REQUESTS HAVING SPATIAL LOCALITY

Low-Latency Bridge to Support Out-of-Order Execution

ADVANCED INITIALIZATION BUS (AIB)

SYSTEMS AND METHODS FOR ON THE FLY ROUTING IN THE PRESENCE OF ERRORS

Scalable Network-on-Chip for High-Bandwidth Memory

Data flow management

A DATA PROCESSING APPARATUS AND METHOD FOR HANDLING STALLED DATA

Victim cache with write miss merging

SYSTEM AND METHOD FOR FACILITATING EFFICIENT EVENT NOTIFICATION MANAGEMENT FOR A NETWORK INTERFACE CONTROLLER (NIC)

Authenticated control sequences to initialize sensors over a multi-target interface bus

Optimizing Portioned Storage Data Delivery

DATA STORAGE DEVICE INCLUDING A SOLID STATE DRIVE

TOUCHUP FOR MEMORY DEVICE USING EMBEDDED ENCODER/DECODER

Interface Module with Low-Latency Communication of Electrical Signals Between Power Domains

ELASTIC BUFFERS

APPARATUSES, SYSTEMS, AND METHODS FOR STORING AND ACCESSING MEMORY METADATA AND ERROR CORRECTION CODE DATA

APPARATUS, METHOD, NON-TRANSITORY COMPUTER-READABLE MEDIUM AND SYSTEM

Multi-Mode Memory Module and Memory Component

Reconfigurable Parallel Processing

STORAGE-INTEGRATED MEMORY EXPANDER, COMPUTING SYSTEM BASED COMPUTE EXPRESS LINK, AND OPERATING METHOD THEREOF

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

SYSTEMS, DEVICES AND METHODS WITH OFFLOAD PROCESSING DEVICES

DRAGONFLY ROUTING WITH INCOMPLETE GROUP CONNECTIVITY

FAT TREE ADAPTIVE ROUTING

METHOD AND SYSTEM FOR FACILITATING LOSSY DROPPING AND ECN MARKING

Bus-based communication system, system-on-chip and method therefor

METHOD AND APPARATUS FOR DATA TRANSFER BETWEEN ACCESSIBLE MEMORIES OF MULTIPLE PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM USING TWO MEMORY TO MEMORY TRANSFER OPERATIONS

Method and System for Integrating Buffer Views into Buffer Access Operations in Reconfigurable Computing Environments

NETWORK CONTROLLER LOW LATENCY DATA PATH

Interface circuit and memory controller

SYSTEMS AND DEVICES FOR ACCESSING A STATE MACHINE

PACKET ROUTING BETWEEN MEMORY DEVICES AND RELATED APPARATUSES, METHODS, AND MEMORY SYSTEMS

Serial peripheral interface with multi-controller daisy chain

DYNAMIC DMA BUFFER MANAGEMENT

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-ALIGNED WRITES

Data Storage Device and Method for Race-Based Data Access in a Multiple Host Memory Buffer System

TECHNIQUES FOR IMPROVED DATA TRANSFER

SYSTEM, DEVICE AND/OR METHOD FOR PROCESSING DIRECT MEMORY ACCESS GATHER AND SCATTER REQUESTS

MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD

COMPOSABLE INFRASTRUCTURE ENABLED BY HETEROGENEOUS ARCHITECTURE, DELIVERED BY CXL BASED CACHED SWITCH SOC

Object-Oriented Memory

Scheduling Processing-in-Memory Transactions

QUAD-CHANNEL MEMORY MODULE

METHOD OF PROCESSING COMPUTATION AND INFORMATION PROCESSING APPARATUS

MULTI-FUNCTION FLEXIBLE COMPUTATIONAL STORAGE DEVICE

COHERENT BLOCK READ FULFILLMENT

BUFFERING ELEMENTS FOR PROCESSING

ACCELERATOR CONTROL SYSTEM, ACCELERATOR CONTROL METHOD AND ACCELERATOR CONTROL PROGRAM

DATA TRANSITION IN HIGHLY PARALLEL DATABASE MANAGEMENT SYSTEM

HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE

First-in, first-out buffer

Methods and apparatus to facilitate atomic operations in victim cache

Object-Oriented Memory Client

Memory having internal processors and data communication methods in memory

METHOD AND SYSTEM FOR OBTAINING OPTIMAL NUMBER OF DMA CHANNELS

Multiple-core memory controller

SYSTEM AND METHOD FOR FACILITATING EFFICIENT UTILIZATION OF AN OUTPUT BUFFER IN A NETWORK INTERFACE CONTROLLER (NIC)

System and method for facilitating self-managing reduction engines

DATA TRANSMISSION DEVICE AND METHOD

PROVIDING LOCATION-BASED PREFETCHING IN PROCESSOR-BASED DEVICES

Memory systems and operating methods thereof

SYSTEM AND METHOD FOR FACILITATING DYNAMIC COMMAND MANAGEMENT IN A NETWORK INTERFACE CONTROLLER (NIC)

METHOD FOR MANAGING MEMORY WRITE REQUEST IN CACHE DEVICE

High capacity memory system using standard controller component

Methods and apparatus for allocation in a victim cache system

Dynamically sized redundant write buffer with sector-based tracking

Dynamic DMA buffer management

LOCAL PAGE WRITES VIA PRE-STAGING BUFFERS FOR RESILIENT BUFFER POOL EXTENSIONS

SYSTEM AND METHOD FOR FACILITATING EFFICIENT ADDRESS TRANSLATION IN A NETWORK INTERFACE CONTROLLER (NIC)

SYSTEM AND METHOD FOR FACILITATING EFFICIENT MESSAGE MATCHING IN A NETWORK INTERFACE CONTROLLER (NIC)

System and method for facilitating operation management in a network interface controller (NIC) for accelerators

SYSTEM AND METHOD FOR FACILITATING FINE-GRAIN FLOW CONTROL IN A NETWORK INTERFACE CONTROLLER (NIC)

INSTRUCTION SET ARCHITECTURE SUPPORT FOR AT-SPEED NEAR-MEMORY ATOMIC OPERATIONS IN A NON-CACHED DISTRIBUTED MEMORY SYSTEM

SYSTEM AND METHOD FOR FACILITATING ON-DEMAND PAGING IN A NETWORK INTERFACE CONTROLLER (NIC)

MEMORY DEVICE PERFORMING SELF-CALIBRATION BY IDENTIFYING LOCATION INFORMATION AND MEMORY MODULE INCLUDING THE SAME

Memory Systems, Modules, and Methods for Improved Capacity

SYSTEM AND METHOD FOR FACILITATING EFFICIENT PACKET FORWARDING USING A MESSAGE STATE TABLE IN A NETWORK INTERFACE CONTROLLER (NIC)

ADDRESS CONVERSION SYSTEM AND ADDRESS CONVERSION METHOD

Hybrid victim cache and write miss buffer with fence operation

Memory modules and systems with variable-width data ranks and configurable data-rank timing

Methods and apparatus for eviction in dual datapath victim cache system

MULTI-PATH UNIVERSAL ASYNCHRONOUS TRANSCEIVER AND TRANSMISSION METHOD THEREOF

ZQ calibration circuit and method for memory interfaces

JUST-IN-TIME (JIT) SCHEDULER FOR MEMORY SUBSYSTEMS

Write merging on stores with different privilege levels

CONTROLLING AGGREGATION FOR HRAM

Systems and Methods for Task Switching in Neural Network Processor

MEMORY DEVICE HARDWARE HOST READ ACTIONS BASED ON LOOKUP OPERATION RESULTS