Controller controlling non-volatile memory device, storage device including the same, and operating method thereof

SWITCH DEVICE FOR FACILITATING SWITCHING IN DATA-DRIVEN INTELLIGENT NETWORK

Configurable types of write operations

SEMICONDUCTOR DEVICE

Memory module threading with staggered data transfers

Memory controller including a write staging buffer to manage write requests for a high capacity memory circuit with large number of independently accessible memory banks

MEMORY CONTROLLER FOR A HIGH CAPACITY MEMORY CIRCUIT USING VIRTUAL BANK ADDRESSING

ALGORITHMS FOR USE OF LOAD INFORMATION FROM NEIGHBORING NODES IN ADAPTIVE ROUTING

Encoding and decoding apparatuses and methods for implementing multi-mode coding

High performance mechanism for exporting peripheral services and offloads using direct memory access (DMA) engine

Atomic compare and swap in a coherent cache system

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Folded memory modules

High-performance, high-capacity memory systems and modules

PARTIAL DATA HANDLING HARDWARE

Methods and apparatus to reduce bank pressure using aggressive write merging

Memory system, memory controller and operation method thereof

Memory system and operating method supporting fast boot using host memory buffer and default enabled information

Memory request priority up-leveling

Interface device having plurality of ports and method of operating the same

SHARED BUFFERED MEMORY ROUTING

INTEGRATED CIRCUIT PAD FAILURE DETECTION

MEMORY CONTROLLER, STORAGE DEVICE, AND METHOD OF OPERATING THE SAME

MULTIPLE CHANNEL DIRECT ACCESS MEMORY-BASED CONFIGURATION SYSTEM

Advanced initialization bus (AIB)

WRITE MERGING ON STORES WITH DIFFERENT TAGS

Apparatuses and methods for input buffer enable clock synchronization

Data flow management

High-throughput low-latency hybrid memory module

Drift detection in timing signal forwarded from memory controller to memory device

System and method for facilitating efficient host memory access from a network interface controller (NIC)

Fully pipelined read-modify-write support

System and method for facilitating data-driven intelligent network

LOCAL NON-VOLATILE MEMORY EXPRESS VIRTUALIZATION DEVICE

COMPOSABLE INFRASTRUCTURE ENABLED BY HETEROGENEOUS ARCHITECTURE, DELIVERED BY CXL BASED CACHED SWITCH SOC AND EXTENSIBLE VIA CXLOVERETHERNET (COE) PROTOCOLS

Memory interface having multiple snoop processors

ENHANCED PERIPHERAL PROCESSING SYSTEM TO OPTIMIZE POWER CONSUMPTION

Methods implementing doorbell register/file identification table with high-speed data communication fabric for cloud gaming data storage and retrieval

MEMORY SYSTEM AND CONTROL METHOD

Memory system and operating method thereof

Method and system for providing network egress fairness between applications

IMPLIED DIRECTORY STATE UPDATES

Fault tolerant memory systems and components with interconnected and redundant data interfaces

Integrating buffer views into buffer access operations in a coarse-grained reconfigurable computing environment

Monolithic serial NOR flash with wide input-output bus

Systems and methods for concurrent logging and event capture

DISKLESS ACTIVE DATA GUARD AS CACHE

Memory Request Timeouts Using a Common Counter

Victim cache that supports draining write-miss entries

Semiconductor device related to calibrating a termination resistance

METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM

Memory system and method of controlling nonvolatile memory

Semiconductor device

Hardware accelerator circuits for near storage compute systems

SYSTEMS AND METHODS FOR ACCELERATING MEMORY TRANSFERS AND COMPUTATION EFFICIENCY USING A COMPUTATION-INFORMED PARTITIONING OF AN ON-CHIP DATA BUFFER AND IMPLEMENTING COMPUTATION-AWARE DATA TRANSFER OPERATIONS TO THE ON-CHIP DATA BUFFER

METHODS AND APPARATUS TO CONFIGURE AN INTEGRATED CIRCUIT USING A DIRECT MEMORY ACCESS CONTROLLER

FAST DATA SYNCHRONIZATION IN PROCESSORS AND MEMORY

METHOD OF RING ALLREDUCE PROCESSING

Application partitioning for locality in a stacked memory system

PERIPHERAL BUS VIDEO COMMUNICATION USING INTERNET PROTOCOL

Electronic device and method for performing garbage collection

Memory and an operating method thereof, a memory system

Integrated circuit that extracts data, neural network processor including the integrated circuit, and neural network device

Fairly utilizing multiple contexts sharing cryptographic hardware

Methods and apparatus to facilitate read-modify-write support in a victim cache

Increased read performance for implementations having multiple interface links

Object-oriented memory client

COMMUNICATION CHIP AND DATA PROCESSING METHOD

Method to improve communication speed in existing control system

Multi-channel system architecture for managing flow of data and associated trace information

Memory system changing write mode and method of controlling nonvolatile memory by changing write mode

Universal data path architecture for different data array

Neural processing accelerator

COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN CROSS VALIDATION PROGRAM, METHOD FOR CROSS VALIDATION, AND INFORMATION PROCESSING APPARATUS

High capacity memory system using standard controller component

Memory system design using buffer(s) on a mother board

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A COHERENT VICTIM CACHE WITH PARALLEL DATA PATHS

SYSTEMS, DEVICES AND METHODS WITH OFFLOAD PROCESSING DEVICES

Systems, methods, and apparatus to enable data aggregation and adaptation in hardware acceleration subsystems

METHOD AND APPARATUS TO RESET COMPONENTS IN A SIDEBAND BUS INTERFACE IN A MEMORY MODULE

Object-oriented memory for client-to-client communications

Computer memory expansion device and method of operation

Information recording method, apparatus, and device, and readable storage medium

Memory device for efficiently determining whether to perform re-training operation and memory system including the same

Randomized data distribution in highly parallel database management system

Coherent block read fulfillment

Virtual partitioning a processor-in-memory (“PIM”)

On-chip packet caching apparatus, method and computer-readable medium using idle address management module

Packet processing system, method and device utilizing a port client chain

Packet processing system, method and device utilizing a port client chain

Packet processing system, method and device utilizing a port client chain

Packet processing system, method and device utilizing a port client chain

Streaming engine with deferred exception reporting

PACKET FORWARDING APPARATUS WITH BUFFER RECYCLING AND ASSOCIATED PACKET FORWARDING METHOD

PCIe communications

Extended cache for efficient object store access by a database

Enterprise host memory buffer for DRAM-less SSD

Enterprise host memory buffer

Controller controlling non-volatile memory device, storage device including the same, and operating method thereof

MEMORY DEVICE AND OPERATION METHOD THEREOF

Storage device for interfacing with host and method of operating the host and the storage device

Integrated circuit and configuration method thereof

Local page writes via pre-staging buffers for resilient buffer pool extensions

Semiconductor memory device and method of controlling the same

Scalable network-on-chip for high-bandwidth memory

Memory access tracking using a peripheral device

Memory device performing self-calibration by identifying location information and memory module including the same

Method for communication between components of an electrical device

Non-volatile dual inline memory module (NVDIMM) for supporting DRAM cache mode and operation method of NVDIMM

Semiconductor memory systems with on-die data buffering

Load reduced nonvolatile memory interface

Duplicated registers in chiplet processing units

Host controller interface using multiple circular queue, and operating method thereof

Atomic operations and histogram operations in a cache pipeline

MANAGING HAZARDS IN A MEMORY CONTROLLER

Using dynamic bursts to support frequency-agile memory interfaces

Dynamically sized redundant write buffer with sector-based tracking

Memory module with reduced read/write turnaround overhead

Dynamic routing of texture loads in graphics processing

Sideband information over host interface considering link states

Arithmetic processing device and memory access method

On-the-fly compression scheme for soft bit data in non-volatile memory

Systems and methods for accelerating memory transfers and computation efficiency using a computation-informed partitioning of an on-chip data buffer and implementing computation-aware data transfer operations to the on-chip data buffer

Non-volatile memory device, method of operating the device, and memory system including the device

Application-transparent near-memory processing architecture with memory channel network

Neural network processor using compression and decompression of activation data to reduce memory bandwidth utilization

Configurable interface circuit

Processor system and method for increasing data-transfer bandwidth during execution of a scheduled parallel process

Command scheduling component for memory

Multiple overlays for use with a data processing array

Memory device for wafer-on-wafer formed memory and logic

Multi-function flexible computational storage device

Signal routing between memory die and logic die for mode based operations

TESTING MEMORY OF WAFER-ON-WAFER BONDED MEMORY AND LOGIC

SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE FOR PERFORMING OPERATIONS

Wafer-on-wafer formed memory and logic for genomic annotations

WAFER-ON-WAFER FORMED MEMORY AND LOGIC

INPUT/OUTPUT CONNECTIONS OF WAFER-ON-WAFER BONDED MEMORY AND LOGIC

Method and system for facilitating lossy dropping and ECN marking

Signal routing between memory die and logic die

SYSTEMS AND METHODS FOR EFFICIENT DATA BUFFERING

STORAGE DEVICE, HOST DEVICE AND DATA TRANSFER METHOD THEREOF

MEMORY INTERFACE WITH REDUCED ENERGY TRANSMIT MODE

Methods and apparatus for allocation in a victim cache system

COMPOSABLE INFRASTRUCTURE ENABLED BY HETEROGENEOUS ARCHITECTURE, DELIVERED BY CXL BASED CACHED SWITCH SOC AND EXTENSIBLE VIA CXLOVERETHERNET (COE) PROTOCOLS

Initializing memory systems

System on chip and method for operating system on chip

Storage device that uses a host memory buffer and a memory management method including the same

Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC

Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC

Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC

Multi-deck memory device including buffer circuitry under array

Automatic read control system based on a hardware accelerated SPI and automatic read control method

Aggressive write flush scheme for a victim cache

Semiconductor device and method for controlling plural chips

MEMORY INCLUSIVITY MANAGEMENT IN COMPUTING SYSTEMS

METHOD FOR ACCESSING FLASH MEMORY AND FLASH MEMORY CONTROLLER AND ELECTRONIC DEVICE THEREOF

CIRCULAR BUFFERING IN NEURAL NETWORK PROCESSOR

Folded memory modules

Multiple function level reset management

Cross bus memory mapping

SEMICONDUCTOR DEVICE

Interface module with low-latency communication of electrical signals between power domains

Mobile IoT edge device using 3D-die stacking re-configurable processor module with 5G processor-independent modem

Multi-mode memory module and memory component

Processing system and corresponding method of operation

Memory module with configurable command buffer

Verification system and verification method for Ethernet interface chip

Methods and apparatus to facilitate atomic operations in victim cache

METHODS FOR INCREASING INTRACELLULAR ACTIVITY OF HSP70

Apparatus and method and computer program product for handling flash physical-resource sets

Interprocessor procedure calls

Accelerating Method of Executing Comparison Functions and Accelerating System of Executing Comparison Functions

Drift detection in timing signal forwarded from memory controller to memory device

Data transmission system and operation method thereof

UNMATCHED ARCHITECTURE COMPENSATION VIA DIGITAL COMPONENT DELAY

Asynchronous communication protocol compatible with synchronous DDR protocol

DATA ACCESS METHOD FOR DIRECT MEMORY ACCESS (DMA), AND PROCESSOR

SYSTEM AND METHOD FOR FACILITATING DATA-DRIVEN INTELLIGENT NETWORK WITH INGRESS PORT INJECTION LIMITS

Apparatus and method for data communications between non-volatile memory devices and a memory controller

Memory devices and methods having multiple acknowledgements in response to a same instruction

Memory having internal processors and data communication methods in memory

Memory system and operating method supporting fast boot using host memory buffer and default enabled information

Methods implementing doorbell register/file identification table with high-speed data communication fabric for cloud gaming data storage and retrieval

Memory module threading with staggered data transfers

Method and apparatus for page validity management and related storage system

METHODS FOR DISTRIBUTING SOFTWARE-DETERMINED GLOBAL LOAD INFORMATION

Firmware update of an interconnect device

Serial communication method and system for memory access

Managing hazards in a memory controller

System and method for facilitating efficient packet forwarding in a network interface controller (NIC)

Fractional sampling-rate converter to generate output samples at a higher rate from input samples

Data circuit for a low swing data bus

Peripheral component interconnect express interface device and method of operating the same

Write merging on stores with different privilege levels

Encoding and decoding apparatuses and methods for implementing multi-mode coding

Neural processing accelerator

Victim cache with write miss merging

Local non-volatile memory express virtualization device

Signal processor, processor system and method for transferring data

Computing system for reducing latency between serially connected electronic devices

SYSTEMS AND METHODS FOR ENABLING CONCURRENT APPLICATIONS TO PERFORM EXTREME WIDEBAND DIGITAL SIGNAL PROCESSING WITH MULTICHANNEL COHERENCY

Write merging on stores with different tags

APPARATUS AND METHOD FOR IMPROVING INPUT/OUTPUT THROUGHPUT OF MEMORY SYSTEM

Systems and devices for accessing a state machine

Offloaded data migration between storage devices

System and method for facilitating efficient utilization of an output buffer in a network interface controller (NIC)

Opportunistic block transmission with time constraints

SYSTEM AND METHOD FOR STORING AND FORWARDING DATA FROM A VITAL-SIGNS MONITOR

Detection of compromised storage device firmware

Data-buffer component with variable-width data ranks and configurable data-rank timing

System and method for facilitating dynamic command management in a network interface controller (NIC)

MEMORY SYSTEM INCLUDING HETEROGENEOUS MEMORIES, COMPUTER SYSTEM INCLUDING THE MEMORY SYSTEM, AND DATA MANAGEMENT METHOD THEREOF

Non-interrupting portable page request interface

Algorithms for use of load information from neighboring nodes in adaptive routing

PIPELINE SETTING SELECTION FOR GRAPH-BASED APPLICATIONS

Systems and methods for per traffic class routing

System and method for facilitating efficient packet forwarding using a message state table in a network interface controller (NIC)

SYSTEM AND METHOD FOR FACILITATING DATA REQUEST MANAGEMENT IN A NETWORK INTERFACE CONTROLLER (NIC)

System and method for facilitating efficient message matching in a network interface controller (NIC)

BUFFER COMMUNICATION FOR DATA BUFFERS SUPPORTING MULTIPLE PSEUDO CHANNELS

Host Memory Buffer (HMB) Abstraction Protocol Layer

Deadlock-free multicast routing on a dragonfly network

System and method for facilitating self-managing reduction engines

High capacity memory system with improved command-address and chip-select signaling mode

Method and system for providing network egress fairness between applications

System and method for facilitating fine-grain flow control in a network interface controller (NIC)

System and method for facilitating data-driven intelligent network with endpoint congestion detection and control

System and method for facilitating data-driven intelligent network with per-flow credit-based flow control

System and method for facilitating tracer packets in a data-driven intelligent network

METHOD AND SYSTEM FOR FACILITATING WIDE LAG AND ECMP CONTROL

Weighting routing

Method, apparatus and system for device transparent grouping of devices on a bus

System and method for facilitating efficient address translation in a network interface controller (NIC)

Memory system and method of controlling nonvolatile memory

System and method for facilitating hybrid message matching in a network interface controller (NIC)

System and method for facilitating efficient load balancing in a network interface controller (NIC)

Switch device for facilitating switching in data-driven intelligent network

System and method for facilitating global fairness in a network

System and method for facilitating data-driven intelligent network with flow control of individual applications and traffic flows

Fat tree adaptive routing

SYSTEM AND METHOD FOR DYNAMIC ALLOCATION OF REDUCTION ENGINES

Systems and methods for on the fly routing in the presence of errors

Memory module, main board, and server device

System and method for facilitating on-demand paging in a network interface controller (NIC)

Methods and apparatus for multi-banked victim cache with dual datapath

Method and system for facilitating write latency reduction in a queue depth of one scenario

Memory access technology and computer system

DYNAMIC BUFFER MANAGEMENT IN DATA-DRIVEN INTELLIGENT NETWORK

System and method for facilitating data-driven intelligent network

System and method for facilitating efficient packet injection into an output buffer in a network interface controller (NIC)

Systems and methods for adaptive routing in the presence of persistent flows

System and method for facilitating efficient management of non-idempotent operations in a network interface controller (NIC)

PROCESSOR ARRANGEMENT FOR MONITORING CONTROL-FLOW INTEGRITY

System and method for facilitating operation management in a network interface controller (NIC) for accelerators

Electronic device

System and method for facilitating efficient event notification management for a network interface controller (NIC)

Just-in-time (JIT) scheduler for memory subsystems

System and method for facilitating efficient host memory access from a network interface controller (NIC)

LATENCY-AWARE PREFETCH BUFFER

System and method for performing on-the-fly reduction in a network

Method and system for providing network ingress fairness between applications

METHOD AND APPARATUS TO PERFORM CYCLIC REDUNDANCY CHECK TRAINING IN A MEMORY MODULE

Semiconductor device

Elastic buffer in a memory sub-system for debugging information

Optimized adaptive routing to reduce number of hops

Data transition in highly parallel database management system

DYNAMIC DMA BUFFER MANAGEMENT

ADAPTIVE PIPELINE SELECTION FOR ACCELERATING MEMORY COPY OPERATIONS

Mapping supporting non-sequential writes at sequentially-written memory devices

Buffer pool maintenance improvement

Object-oriented memory for client-to-client communications

Object-oriented memory client

Sparse matrix multiplication acceleration mechanism

Memory system and information processing system

Dragonfly routing with incomplete group connectivity

Direct network access by a memory mapped peripheral device for scheduled data transfer on the network

Head of line entry processing in a buffer memory device

Effective PCIe utilization by PCIe TLP coalescing

Transaction identification

Integrated circuit I/O integrity and degradation monitoring

MEMORY SYSTEM

Dynamic sequencing of data partitions for optimizing memory utilization and performance of neural networks

Buffer IC with asymmetric memory module interfaces

Readable data determination

STORAGE SYSTEM

Modular sequencer for radar applications

Method and apparatus for detecting ATS-based DMA attack

Draining operation to cause store data to be written to persistent memory

SYSTEM, APPARATUS AND METHODS FOR DIRECT DATA READS FROM MEMORY

Storage device for moving valid data to an open memory block based on a valid page list and operating method thereof

Storage device and method for updating meta slice including map chunks stored in nonvolatile memory device according to journal entries

Reconfigurable hardware buffer in a neural networks accelerator framework

Reconfigurable parallel processing

Method for PRP/SGL handling for out-of-order NVME controllers

Memory system and method of controlling nonvolatile memory

Data loading and storage system and method

Dedicated design for testability paths for memory sub-system controller

Interfacing with systems, for processing data samples, and related systems, methods and apparatuses

PREFETCHING FROM INDIRECT BUFFERS AT A PROCESSING UNIT