190350 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
Sub-classes:MICRO-CONTROLLER SYSTEM AND METHOD FOR WAKING UP THE CENTRAL PROCESSING UNIT
#2TECHNOLOGIES FOR INTERCONNECT ADDRESS REMAPPER WITH EVENT RECOGNITION AND REGISTER MANAGEMENT
#3DATA BURST QUEUE MANAGEMENT
#4CONFIGURABLE INTERCONNECT ADDRESS REMAPPER WITH EVENT RECOGNITION
#5Remote direct memory access operations with integrated data arrival indication
#6SECURE VIRTUAL MACHINE AND PERIPHERAL DEVICE COMMUNICATION
#7MEMORY DEVICE WITH EMBEDDED DEEP LEARNING ACCELERATOR IN MULTI-CLIENT ENVIRONMENT
#8Data burst queue management
#9DATA TRANSFER DEVICE AND DATA TRANSFER METHOD
#10SECURE VIRTUAL MACHINE AND PERIPHERAL DEVICE COMMUNICATION
#11Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options
#12Motor driver and control method thereof and motor driving system
#13Quality of service control of logical devices for a memory sub-system
#14Online upgrading method and system for multi-core embedded system
#15Transfer device, information processing device, and data transfer method
#16Data frame interface network device
#17Quality of service control of logical devices for a memory sub-system
#18Robust sensor timestamp management
#19Dynamic assignment of interrupts based on input/output metrics
#20Live updates for virtual machine monitor
#21Information processor with tightly coupled smart memory unit
#22Interface for memory having a cache and multiple independent arrays
#23Master chip, slave chip, and inter-chip DMA transmission system
#24Driver for network timing systems
#25Semiconductor device
#26Memory controller and method of operating the same
#27Controller-mediated volume transformation in a shared-resource environment
#28Interface for memory having a cache and multiple independent arrays
#29Live updates for virtual machine monitor
#30Semiconductor integrated circuit device and method for comparing data
#31System and method for virtual machine live migration
#32SEMICONDUCTOR APPARATUS
#33Forced detaching of applications from DMA-capable PCI mapped devices
#34Controller-mediated volume transformation in a shared-resource environment
#35Computer device and method for reading or writing data by computer device
#36Deterministic control system for the operation of data transfer means by direct memory access
#37METHODS AND SYSTEMS FOR ACHIEVING TRUSTED FAULT TOLERANCE OF A SYSTEM OF UNTRUSTED SUBSYSTEMS
#38Facilitating execution-aware hybrid preemption for execution of tasks in computing environments
#39Data communication interface for processing data in low power systems
#40Producer/consumer remote synchronization
#41SR-IOV-supported storage resource access method and storage controller and storage device
#42Controller-mediated volume transformation in a shared-resource environment
#43Data coherency model and protocol at cluster level
#44Interrupt management system for deferring low priority interrupts in real-time system
#45Delivering interrupts through non-transparent bridges in a PCI-express network
#46DMA controller for a data processing system, a data processing system and a method of operating a DMA controller
#47Information processor with tightly coupled smart memory unit
#4812C bus controller slave address register and command FIFO buffer
#49Interrupt-driven I/O arbiter for a microcomputer system
#50Processor model using a single large linear registers, with new interfacing signals supporting FIFO-base I/O ports, and interrupt-driven burst transfers eliminating DMA, bridges, and external I/O bus
#51Transmitting inter-processor interrupt messages by privileged virtual machine functions
#52Caching methods and systems using a network interface card
#53Methods and systems for accessing storage using a network interface card
#54System internal latency measurements in realtime applications
#55Logical-to-physical block mapping inside the disk controller: accessing data objects without operating system intervention
#56Information processor with tightly coupled smart memory unit
#57Managing message signaled interrupts in virtualized computer systems
#58Method and apparatus for adaptive data chunk transfer
#59System and method for input/output acceleration device having storage virtual appliance (SVA) using root of PCI-E endpoint
#60Enhanced I/O performance in a multi-processor system via interrupt affinity schemes
#61Service processor (SP) initiated data transaction with bios utilizing interrupt
#62COMPUTING SYSTEM AND OPERATING METHOD OF THE SAME
#63Host controller
#64Firmware interface with backup non-volatile memory storage
#65Virtualizing input/output interrupts
#66Technologies for moderating packet ingress interrupt generation
#67Sharing message-signaled interrupts between peripheral component interconnect (PCI) I/O devices
#68Sharing message-signaled interrupts between peripheral component interconnect (PCI) I/O devices
#69Picoblaze processor based multifunction vehicle bus (pMVB) controller system
#70Coalescing stages in a multiple stage completion sequence
#71Data transmission method for improving DMA and data transmission efficiency based on priorities of at least two arbitration units for each DMA channel
#72Polling determination
#73System on chip and method of operating a system on chip
#74RFID interface and interrupt
#75Universal serial bus (USB) device access from one or more virtual machines
#76Semiconductor apparatus
#77APPARATUS AND METHOD FOR SENSING OBJECT STATE
#78SMART DIRECT MEMORY ACCESS
#79Data coherency model and protocol at cluster level
#80Method and apparatus for delivering MSI-X interrupts through non-transparent bridges to computing resources in PCI-express clusters
#81Support for IOAPIC interrupts in AMBA-based devices
#82Providing real-time interrupts over ethernet
#83Information-processing apparatus, information-processing method, and program
#84System and method for virtual machine live migration
#85Data processing
#86Memory module communication control
#87Memory module communication control
#88System method for managing USB data transfers by sorting a plurality of endpoints in scheduling queue in descending order based partially on endpoint frequency
#89Universal serial bus device and method for controlling an idle-delay time thereof
#90Expander interrupt processing
#91Motor control apparatus and motor control method
#92Bridging and integrating devices across processing systems
#93Power-optimized interrupt delivery
#94Counter for fast interrupt register access in hypervisors
#95Injecting interrupts in virtualized computer systems
#96Write transaction interpretation for interrupt assertion
#97Memory bus attached input/output (‘I/O’) subsystem management in a computing system
#98Memory bus attached input/output (‘I/O’) subsystem management in a computing system
#99I2C controller register, control, command and R/W buffer queue logic
#100Machine to machine development environment
#101Method and device for providing high speed data transmission with video data
#102Automating digital display
#103DATA TRANSMISSION APPARATUS, SYSTEM, AND METHOD
#104Providing real-time interrupts over Ethernet
#105Virtual system management mode device and control method thereof
#106Information processing system
#107USB class protocol modules
#108Host-based messaging framework for PCIE device management
#109Host controller
#110Method and system for dynamically managing a bus of a portable computing device
#111Microcomputer
#112Processor with tightly coupled smart memory unit
#113Power-optimized interrupt delivery
#114System, processor, apparatus and method for inter-processor communication
#115Host-based messaging framework for PCIe device management
#116Enhanced I/O performance in a multi-processor system via interrupt affinity schemes
#117DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR
#118DMA CONTROLLER, INFORMATION PROCESSING DEVICE AND DMA MANAGEMENT METHOD
#119Host controller
#120Method and apparatus for adaptive data chunk transfer
#121Information-processing apparatus, information-processing method, and program
#122BUS BRIDGE APPARATUS AND BUS BRIDGE SYSTEM
#123Apparatus and method for processing high speed data using hybrid DMA
#124Method and apparatus for indirect interface with enhanced programmable direct port
#125Direct memory access system
#126System for communicating command parameters between a processor and a memory flow controller
#127Interfacing incompatible signaling using generic I/O and interrupt routines
#128Method and system for generating a DMA controller interrupt
#129Method and apparatus for controlling direct memory access
#130Activator, DMA transfer system, DMA transfer method
#131System and method for communicating command parameters between a processor and a memory flow controller
#132High-speed input/output signaling mechanism using a polling CPU and cache coherency signaling
#133Race free data transfer algorithm using hardware based polling
#134Data transfer control device with state transition control and electronic equipment
#135Including descriptor queue empty events in completion events
#136Multiprocessor system comprising an observation element
#137SYSTEM AND METHOD OF AUTOMATICALLY EXECUTING ATA/ATAPI COMMANDS
#138Isolation of input/output adapter interrupt domains
#139Data transfer method for Universal Serial Bus device
#140Driver for network timing system
#141Use of interrupt memory for communication via PCIe communication fabric
#142System and method for controlling flow of data through a buffer to increase time a bridge is in a low power state
#143OS bypass inter-processor interrupt delivery mechanism