190351 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
Distributed control system and semiconductor inspection apparatus including same
#2Scalable round-robin arbiter tree for round-robin arbitration
#3Delivering interrupts to user-level applications
#4Delivering interrupts to user-level applications
#5Virtual machine monitor interrupt support for computer processing unit (CPU)
#6Delivering interrupts to user-level applications
#7Memory access system, method for controlling the same, computer-readable storage medium, and image forming apparatus
#8Application processor and integrated circuit including interrupt controller
#9System arbiter with programmable priority levels
#10Network interface card rate limiting
#11Interrupt-controlled direct memory access peripheral data transfer
#12Delivering interrupts to user-level applications
#13Hierarchical in-memory sort engine
#14Bus relay device for relaying communication through bus of I/O apparatus and CPU wherein relay device has lower side transmission unit to transmit interrupt factor address
#15Multicore processor system, computer product, assigning method, and control method
#16Direct memory access controller
#17Network interface card rate limiting
#18Clock control for DMA busses
#19Polling determination
#20Updating virtual machine memory by interrupt handler
#21Computer system and control method thereof
#22DMA CONTROLLER AND DATA READOUT DEVICE
#23Polling determination
#24Methods and apparatus for interleaving priorities of a plurality of virtual processors
#25Interrupt latency performance counters
#26Information processing apparatus, information processing method, computer-readable recording medium having stored therein program
#27Bridge device with an error tolerant DMA transfer function
#28Computer system and control method thereof
#29BIT SLICE ROUND ROBIN ARBITER
#30Clock control for DMA busses
#31Direct memory access controller
#32Direct memory access controller
#33DMA transfer system using virtual channels
#34Setting bandwidth limiter and adjusting execution cycle of second device using one of the GBL classes selected based on priority of task from first device
#35DMA controller having programmable channel priority
#36Systems and methods for coalescing interrupts
#37Burst buffer appliance comprising multiple virtual machines