DUAL VOLTAGE COMMUNICATION BUS

Host device, slave device, and removable system

System comprising a master device and a slave device having multiple integrated circuit die, wireless communication unit and method therefor

Systems and methods for hardware arbitration of a communications bus

Method for using shared device and resource sharing system

Bus serialization for devices without multi-device support

Method and apparatus for switching state

Exascale fabric time synchronization

Arbiter verification

SPI Interface With Slave-Select Fault Detection And Status Signal

Enhanced serial peripheral interface with hardware flow-control

AUDIO BUS INTERRUPTS

OPTIMAL LATENCY PACKETIZER FINITE STATE MACHINE FOR MESSAGING AND INPUT/OUTPUT TRANSFER INTERFACES

SYSTEM IS APPLIED TO CONTROL INDICATOR LIGHTS FOR NON-VOLATILE MEMORY EXPRESS SOLID STATE DISK

Systems and methods for transmitting an access request via a flexible register access bus

Super hub system and the method thereof

Bus system

Non-linear transmit biasing for a serial bus transmitter

Automatic master-slave system and approach

System for monitoring a to-be-monitored unit of a rack/chassis management controller (RMC/CMC) according to heartbeat signals for determining operating modes

Methods and apparatus for reducing power consumption within embedded systems

Techniques for inter-component communication based on a state of a chip select pin

RELAY APPARATUS AND RELAY METHOD

Monolithically integrated system on chip for silicon photonics

Apparatus and method for autodetection of HART devices over PROFIBUS

Expander device and method for data communication within inter-integrated (IC) system

Power control method and apparatus for low power system of electronic device

Sensor bus interface for electronic devices

DECODER FOR A MODEL TRAIN AND METHOD OF OPERATING A DECODER FOR A MODEL TRAIN

Interface circuit

Sensor systems and methods utilizing adaptively selected carrier frequencies

Communication system, communication system control method, and program

BUS SYSTEM

IDENTIFYING MULTIPLE IDENTICAL DEVICES ON A SHARED BUS

SEMICONDUCTOR APPARATUS AND STATUS CONTROL METHOD OF SEMICONDUCTOR APPARATUS

Core ID designation system for dynamically designated bootstrap processor

Power Saving Methodology for Storage Device Equipped with Task Queues

Gesture recognition for on-board display

Emulating bi-directional bus communication using separate unidirectional channels

Electronic device and data exchange method including protocol indicative of modes of operation

MANAGING AND REVOKING POWER ALLOCATED THROUGH BUS INTERFACES

Storage device having master and slave storage device modes

Enhanced queue management

Dynamic addressing

Systems and methods for aggregating data packets in a mochi system

Interface circuit, method and device for state switching

Systems and methods for performing unknown address discovery in a MoChi space

Systems and methods for implementing topology-based identification process in a MoChi environment

Systems and methods for transmitting interrupts between nodes

Methods and apparatus for accelerating list comparison operations

Flash controller to provide a value that represents a parameter to a flash memory

Memory controller that calibrates a transmit timing offset

Single-wire interface bus transceiver system based on I2C-bus, and associated method for communication of single-wire interface bus

Inter-component communication including posted and non-posted transactions

System and method of monitoring a serial bus

Embedded storage device including a plurality of storage units coupled via relay bus

System bus transaction queue reallocation

Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state

DYNAMICALLY CONFIGURE CONNECTION MODES ON A SYSTEM BASED ON HOST DEVICE CAPABILITIES

CIRCUIT, METHOD, AND DEVICE FOR WAKING UP MASTER MCU

Automatic cascaded address selection

Access and protection of I2C interfaces

I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator

Test for 50 nanosecond spike filter

Secure access to peripheral devices over a bus

System on chip including clock management unit and method of operating the system on chip

Methods and apparatus for a multiple master bus protocol

Propagation of updates to per-core-instantiated architecturally-visible storage resource

Apparatus and method for multi-master solution on MDIO communication bus

Power supply system of electronic device

Multi-master bus

Memory subsystem and computer system

Memory subsystem and computer system

Computing architecture with peripherals

Asynchronous transceiver for on-vehicle electronic device

VEHICLE APPLICATION STORE FOR CONSOLE

PLL system with master and slave devices

Semiconductor device

Method and system for address decoding in a data communications system using a serial data transfer bus

Master/slave management for redundant process controller modules

Low-pin microcontroller device with multiple independent microcontrollers

Low-pin microcontroller device with multiple independent microcontrollers

Controller, bus circuit, control method, and recording medium

HIGH FREQUENCY APPARATUS AND METHOD FOR CONTROLLING HIGH FREQUENCY APPARATUS

Semiconductor device including plurality of function blocks and operating method thereof

Automatic and adaptive selection of multimedia sources

Bus node and bus system and method for identifying the bus nodes of the bus system

System including interface circuit for driving data transmission line to termination voltage

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, AND EXCLUSIVE CONTROL PROGRAM

System and method for tracking peripheral proximity by multiple masters

Communication system for inter-chip communication

Method and apparatus for scheduling blocking tasks

Signal count reduction between semiconductor dies assembled in wafer-level package

System on a chip comprising an I/O steering engine

Universal serial bus (USB) hub for switching downstream ports between host mode and slave mode

Interface circuit for high speed communication, and semiconductor apparatus and system including the same

Method and device for implementing LTE baseband resource pool

12C bus controller slave address register and command FIFO buffer

Voltage mode and current mode device enumeration

Interrupt-driven I/O arbiter for a microcomputer system

Method and apparatus to enable multiple masters to operate in a single master bus architecture

Access and protection of I2C interfaces

COMMUNICATION CONTROLLER FOR ELECTRONIC DEVICES

Method and circuit arrangement for protecting against scanning of an address space

Interconnect and method of operation of an interconnect for ordered write observation (OWO)

Master control board that switches transmission channel to local commissioning serial port of the master control board

Electronic device coupling system and method

Computer system and coupling configuration control method

Connection device

PROGRAMMING HARDWARE REGISTERS USING A PIPELINED REGISTER BUS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES

Data communication device and method for data communication

Low cost low overhead serial interface for power management and other ICs

Access and protection of I2C interfaces

Associating process priority with I/O queuing

Computing architecture with peripherals

Bus serialization for devices without multi-device support

Bus serialization for devices without multi-device support

Control device for IC slave device

Arbitrated access to resources among multiple devices

ELECTRONIC DEVICE ASSEMBLY

Slave side bus arbitration

Distributed timer subsystem

Register access control among multiple devices

System on chip having semaphore function and method for implementing semaphore function

Systems and an apparatus with a sideband interface interconnecting agents with at least one router

Simultaneous edge toggling immunity circuit for multi-mode bus

Predefined static enumeration for dynamic enumeration buses

Multicore bus architecture with non-blocking high performance transaction credit system

Chip synchronization by a master-slave circuit

Memory server with read writeable non-volatile memory

Transaction response modification within interconnect circuitry

Data access protection for computer systems

Single-wire communication with adaptive start-bit condition

Data access protection for computer systems

Slave device for a serial synchronous full duplex bus system

Method of controlling direct memory access of a peripheral memory of a peripheral by a master, an associated circuitry, an associated device and an associated computer program product

Advanced Power Strip

Hardware data structure for tracking partially ordered and reordered transactions

BUS MASTER, BUS SYSTEM, AND BUS CONTROL METHOD

MASTER DEVICE, SLAVE DEVICE AND COMPUTING METHODS THEREOF FOR A CLUSTER COMPUTING SYSTEM

Dynamic address change optimizations

Wired communication with remote function calls

Arbitration and hazard detection for a data processing apparatus

Two-wire communication systems and applications

Electronic device, communication control circuit, and communication control method

Distributed audio coordination over a two-wire communication bus

Peripheral device diagnostics and control over a two-wire communication bus

Subsystem Peripheral Ownership Scheduling and Reconfiguration for Highly Integrated System on Chips

System-on-chip including asynchronous interface and driving method thereof

Programmable address-based write-through cache control

Bus system in SoC

Flash controller to provide a value that represents a parameter to a flash memory

Systems and methods for chip to chip communication

METHOD AND DEVICE FOR FILTERING TRANSACTIONS FOR AN ON-CHIP SYSTEM

METHOD FOR MONITORING COMMUNICATIONS FOR AN ON-CHIP SYSTEM

Bandwidth control method for an on-chip system

Flash memory controller with calibrated data communication

IMAGE DISPLAYING METHOD AND MASTER MOBILE DEVICE

NETWORK POWER MANAGEMENT SYSTEM

Bus controller, data forwarding system, and method for controlling buses

Bridging inter-bus communications

METHOD AND CIRCUIT ARRANGEMENT FOR ACCESSING SLAVE UNITS IN A SYSTEM ON CHIP IN A CONTROLLED MANNER

Multi-protocol serial nonvolatile memory interface

Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media

Method of Transaction and Event Ordering within the Interconnect

MEMORY MECHANISM FOR PROVIDING SEMAPHORE FUNCTIONALITY IN MULTI-MASTER PROCESSING ENVIRONMENT

Time-constrained data copying between storage media

Dynamically adjustable multi-line bus shared by multi-protocol devices

Tunneling messages over an USB to control power delivery

COMMUNICATION SYSTEM AND ELECTRONIC CIRCUIT

Seamless addition of high bandwidth lanes

Master bus device for a vehicle communication bus of a motor vehicle

Safety node in interconnect data buses

Dynamic data collection communication between adapter functions

Connecting multiple slave devices to single master controller in bus system

Electronic device with enhanced management data input/output control

METHOD AND APPARATUS FOR PROCESSING DATA

Slave communication device and bus communication system

Switch monitoring system

BUS CONNECTION CIRCUIT, SEMICONDUCTOR DEVICE AND OPERATION METHOD OF BUS CONNECTION CIRCUIT FOR MAKING PROCEDURE FOR SWITCHING BETWEEN A 1-CYCLE TRANSFER AND A 2-CYCLE TRANSFER UNNECESSARY

Wireless music playback

METHOD AND APPARATUS FOR GENERATING SLAVE DEVICE IDENTIFIER

Intelligent connector

System and method to address devices connected to a bus system

Methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system

Methods to send extra information in-band on inter-integrated circuit (I2C) bus

DETERMINATION OF THE STATE OF AN I2C BUS

Methods to send extra information in-band on inter-integrated circuit (I2C) bus

SECURING SHARED INTERCONNECT FOR VIRTUAL MACHINE

Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

Connectivity of slave devices in mobile devices

Devices with arbitrated interface busses, and methods of their operation

METHODS AND APPARATUS RELATED TO BUS ARBITRATION WITHIN A MULTI-MASTER SYSTEM

Data transmission method for improving DMA and data transmission efficiency based on priorities of at least two arbitration units for each DMA channel

Backplane bus structure of communication system and board recognition method using same

Multiprocessor system

METHOD AND APPARATUS USING HIGH-EFFICIENCY ATOMIC OPERATIONS

System and method for improving ECC enabled memory timing

System interconnect and operating method of system interconnect

RFID interface and interrupt

Device identification generation in electronic devices to allow external control of device identification for bus communications identification, and related systems and methods

Substrate treatment apparatus that controls respective units by master-slave method

Pad direct memory access interface

Distributed I/O control system, distributed I/O control method, and master station and slave station for distributed I/O control system

Chip storing a value that represents adjustment to output drive strength

Device, method and system for operation of a low power PHY with a PCIe protocol stack

Chip having port to receive value that represents adjustment to output driver parameter

Techniques for inter-component communication based on a state of a chip select pin

Chip having port to receive value that represents adjustment to transmission parameter

Inter-component communication including posted and non-posted transactions

Receive clock calibration for a serial bus

Data processing system and method for handling multiple transactions using a multi-transaction request

Inter-component communication including slave component initiated transaction

Inter-component communication including posted and non-posted transactions

Start of sequence detection for one wire bus

Universal bus in the car

Power management system for a bus interface system

System, apparatus and method for centralized management of security inspection devices via field bus network

Microcontroller peripheral data transfer redirection for resource sharing

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Synchronous BMC configuration and operation within cluster of BMC

SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS

Method and device for LIN master and identical LIN slaves data communication in motor vehicles

I2C router system

System bus transaction queue reallocation

Embedded storage device including a plurality of storage units coupled via relay bus

Synchronizing transactions for a single master over multiple busses

Use of an IO link for linking field devices

Field bus system

Control circuitry module group, electric device and modem device

Hardware first come first serve arbiter using multiple request buckets

Intelligent connector and bus controller

Dynamic data collection communication between adapter functions

Inter-component communication using an interface including master and slave communication

Method and system for processing data conflict

Data storage expanding apparatus

Server system for switching master and slave devices

COEXISTENCE OF I2C SLAVE DEVICES AND CAMERA CONTROL INTERFACE EXTENSION DEVICES ON A SHARED CONTROL DATA BUS

Gesture recognition for on-board display

Serial interface systems and methods having multiple modes of serial communication

Snoop and replay for completing bus transaction

Selective designation of multiple cores as bootstrap processor in a multi-core microprocessor

Dynamic reconfiguration of multi-core processor

Inter-core communication via uncore RAM

Multi-core hardware semaphore in non-architectural address space

Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor

Multi-core processor having control unit that generates interrupt requests to all cores in response to synchronization condition

Peripheral equipment control device and information processing

BUS CONNECTION PROGRAM AND APPARATUS

Dynamic shifting of service bus components

Inferring physical layer connection status of generic cables from planned single-end connection events

Universal console chassis for the car

Information handling system docking with coordinated power and data communication

Storage apparatus, and system and method for executing access operations

IMPLEMENTING REMOTE TRANSACTION FUNCTIONALITIES BETWEEN DATA PROCESSING NODES OF A SWITCHED INTERCONNECT FABRIC

Location information exchange between vehicle and device

SYSTEM AND METHOD FOR CONTROLLING A BUS IN RESPONSE TO AN INDICATION OF BUS CAPACITY IN A PORTABLE COMPUTING DEVICE

Camera control interface extension bus

Camera control interface extension bus

Camera control interface extension bus

Dynamic address change optimizations

Backplane timing distribution

System and method for a bus interface

Method and system for using feedback information for selecting a routing bus for a memory transaction

Slave control device and method for programming a slave control device

RELAY DEVICE AND RELAY METHOD

Local bypass for in memory computing

Arbiter for asynchronous state machines

Local bypass in memory computing

Enhanced queue management

Method, apparatus, and system for improving inter-chip and single-wire communication for a serial interface

Providing multiple decode options for a system-on-chip (SoC) fabric

Supporting multiple channels of a single interface

Systems and methods for master arbitration

Priority based connection arbitration in a SAS topology to facilitate quality of service (QoS) in SAS transport

RESTORING STABILITY TO AN UNSTABLE BUS

Methods and systems for interconnecting host and expansion devices within system-in-package (SiP) solutions

Data processing device and data processing method

Credit based low-latency arbitration with data transfer

METHOD, APPARATUS, SYSTEM FOR INCLUDING INTERRUPT FUNCTIONALITY IN SENSOR INTERCONNECTS

Requests and data handling in a bus architecture

Access control to a jointly exclusively usable transmission medium

Apparatus for multiple bus master engines to share the same request channel to a pipelined backbone

Interconnection of multiple chips in a package

Single wire serial interface master module and method thereof for sampling data information

Multiprocessor system with interrupt distributor

Device presence detection using a single channel of a bus

REGULATING ACCESS TO SLAVE DEVICES

CAN bus edge timing control for dominant-to-recessive transitions

Method of performing collective communication according to status-based determination of a transmission order between processing nodes and collective communication system using the same

Providing a fine-grained arbitration system

Bus system including a master device, a slave device, an interconnector coupled between the master device and the slave device, and an operating method thereof

I2C BUS STRUCTURE AND DEVICE AVAILABILITY QUERY METHOD

I2C BUS STRUCTURE AND ADDRESS MANAGEMENT METHOD

Connecting multiple slave devices to a single master controller in bus system

SATA data appliance for providing SATA hosts with access to a configurable number of SATA drives residing in a SAS topology

Data processing device and data processing method

COMMUNICATION SYSTEM

Bus detection and control method and bus detection and control device and mobile industry processor interface system thereof

Managing access to shared buffer resources