Processor and control method for processor

Gang programming of devices

Two-wire communication protocol engine

Master mode and slave mode of computing device

Network on a chip socket protocol

Providing a serial download path to devices

Combination of error correction and error detection for transmitting digital data

Barrier transactions in interconnects

Prediction of electronic component behavior in bus-based systems

DATA ROUTING SYSTEM SUPPORTING DUAL MASTER APPARATUSES

Bus system having a master and a group of slaves and communication method for interchanging data in said bus system

Configurable Response Generator for Varied Regions of System Address Space

Bus arbitration apparatus provided to a bus connected to a plurality of bus masters, bus arbitration method, and computer-readable storage medium

Arbiter for asynchronous state machines

Arbitration circuity and method for arbitrating between a plurality of requests for access to a shared resource

System and method to address devices connected to a bus system

System on chip for enhancing quality of service and method of controlling the same

Apparatus and method for providing a bidirectional communications link between a master device and a slave device

DATA PROCESSING DEVICE AND METHOD FOR CONTROLLING DATA PROCESSING DEVICE

Method and Circuit Arrangement for Transmitting Data Between Processor Modules

Information processing apparatus and control method

IMAGE PROCESSING APPARATUS

Information processing system

Pipe arbitration using an arbitration circuit to select a control circuit among a plurality of control circuits and by updating state information with a data transfer of a predetermined size

Apparatuses for inter-component communication including slave component initiated transaction

System and method for a bus interface

Semiconductor device

Switch fabric having a serial communications interface and a parallel communications interface

Vehicle comprising multi-operating system

TRANSPONDER, METHOD AND RECORDING MEDIUM CONTAINING INSTRUCTIONS FOR CONTROLLING THE SAME

Method and device for transmitting data having a variable bit length

Universal bus in the car

Method and system for vehicle data collection

I/O virtualization and switching system

Gesture recognition for on-board display

Proximity warning relative to other cars

VEHICLE APPLICATION STORE FOR CONSOLE

CONTROL OF DEVICE FEATURES BASED ON VEHICLE STATE

Microcontroller including alternative links between peripherals for resource sharing

Object sensing (pedestrian avoidance/accident avoidance)

Street side sensors

Vehicle climate control

Configurable vehicle console

Behavioral tracking and vehicle applications

Car location

In-car communication between devices

Sharing applications/media between car and phone (hydroid)

Mobile hot spot/router/application share site or network

Parking space finder based on parking meter data

Method and system for maintaining and reporting vehicle occupant information

In-cloud connection for car multimedia

Etiquette suggestion

Parking meter expired alert

Universal console chassis for the car

METHOD OF TRANSACTION AND EVENT ORDERING WITHIN THE INTERCONNECT

Methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system

Method for scheduling bus system transmissions

Systems and methods for wireless music playback

Bus connection circuit, semiconductor device and operation method of bus connection circuit for making procedure for switching between a 1-cycle transfer and a 2-cycle transfer unnecessary

Providing multiple decode options for a system-on-chip (SoC) fabric

Supporting multiple channels of a single interface

Aggregating completion messages in a sideband interface

Dynamically determining a primary or slave assignment based on receiving a power signal from the cable at the port of a device

Dynamic address change optimizations

Providing adaptive bandwidth allocation for a fixed priority arbiter

Semiconductor integrated circuit apparatus

Multi-master bus architecture for system-on-chip

Dynamic resource allocation for transaction requests issued by initiator devices to recipient devices

Bus system in SoC and method of gating root clocks therefor

Scalable processing unit

Adaptable video architectures

BIT SLICE ROUND ROBIN ARBITER

Requests and data handling in a bus architecture

System and method for improving ECC enabled memory timing

Control panel and serial port communication arbiter for touch screen with camera

Providing multiple communication protocols for a control system having a master controller and a slave controller

Integer and half clock step division digital variable clock divider

Avoiding non-posted request deadlocks in devices by holding the sending of requests

Avoiding non-posted request deadlocks in devices by holding the sending of requests

System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecture

Method and system for receiving commands using a scoreboard on an infiniband host channel adaptor

System and method for allocating transaction ID in a system with a plurality of processing modules

Managing bandwidth allocation in a processing node using distributed arbitration

Lookahead Priority Collection to Support Priority Elevation

Chip having register to store value that represents adjustment to reference voltage

Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performance

Memory system with calibrated data communication

Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines

Priority based exception mechanism for multi-level cache controller

Programmable mapping of external requestors to privilege classes for access protection

Cache pre-allocation of ways for pipelined allocate requests

Memory attribute sharing between differing cache levels of multilevel cache

Mechanism to Update the Status of In-Flight Cache Coherence In a Multi-Level Cache Hierarchy

Programmable address-based write-through cache control

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Hazard prevention for data conflicts between level one data cache line allocates and snoop writes

Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system

Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU

Floating point multiplier circuit with optimized rounding calculation

Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme

Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers

Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stalls

Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty

Distributed user controlled multilevel block and global cache coherence with accurate completion status

Apparatus and methods for serial interfaces

Electrical circuit for transmitting signals between two masters and one or more slaves

Round robin arbiter with mask and reset mask

Interface system, and corresponding integrated circuit and method

Memory interleaving device to re-order messages from slave IPS and a method of using a reorder buffer to re-order messages from slave IPS

Power management device with communications capability and method of use

Arbitration circuit and control method thereof

Device for arbitrating bus accesses and method for controlling same

Resolving address conflicts for master-slave communications over a single-wire bus between a master circuit and at least two slave circuits

Formal verification of random priority-based arbiters using property strengthening and underapproximations

Bus-system including an interconnector, a master device, a slave device, and an operating method thereof

Bus arbitration apparatus and bus arbitration method

Dual register data path architecture with registers in a data file divided into groups and sub-groups

Cache with multiple access pipelines

Transaction info bypass for nodes coupled to an interconnect fabric

Interleaved Memory Access from Multiple Requesters

Requester based transaction status reporting in a system with multi-level memory

Closed loop adaptive voltage scaling

Communication system, master device and slave device, and communication method, configured to handle plural concurrent requests

Providing a fine-grained arbitration system

Network remote power management outlet strip

BUS ARBITRATION APPARATUS

Single wire bus communication protocol

Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform

Networkable electrical power distribution plugstrip with current display and method of use

Method and system for address allocation for a plurality of devices connected to a multi-master bus

Memory controller and method utilizing equalization co-efficient setting

Semiconductor device

Arbitrator and arbitrating method applied to system management bus system

Requests and data handling in a bus architecture

Pin multiplexing

System and method for dynamically configuring processing resources and memory resources of wireless-enabled components

Wireless bus for intra-chip and inter-chip communication, including wireless-enabled component (WEC) embodiments

Wireless bus for intra-chip and inter-chip communication, including scalable wireless bus embodiments

System having co-located functional resources and applications thereof

Creating a system on the fly and applications thereof

ADAPTIVE BANDWIDTH ALLOCATION FOR MEMORY

Bus arbitration for sideband signals

Network Power Management System

System and method for communicating on an electrical bus

Multi-processor system and controlling method thereof

Synchronising activities of various components in a distributed system

Data store maintenance requests in interconnects

UTILIZATION-ENHANCED SHARED BUS SYSTEM AND BUS ARBITRATION METHOD

Communications control bus and apparatus for controlling multiple electronic hardware devices

Circuit and method for pipe arbitration using available state information and arbitration

Maintaining required ordering of transaction requests in interconnects using barriers and hazard checks

Barrier transactions in interconnects

Reduced latency barrier transaction requests in interconnects

Method and device for priority generation in multiprocessor apparatus

BUS ARBITRATION CIRCUIT AND BUS ARBITRATION METHOD

Method and system for bus arbitration

Preventing hangs in a system with synchronized operation using stalls

Bus arbitration system, a method of connecting devices of an IC employing a bus system and an IC

Device having priority upgrade mechanism capabilities and a method for updating priorities

Controlling bus access

BUS ARBITER AND BUS SYSTEM

Memory access controller, system, and method

Method for Accessing a Data Transmission Bus, Corresponding Device and System

Architecture for a message bus

Method and system for selecting a communications bus system as a function of an operating mode

Associating process priority with I/O queuing

Method and system of reducing latencies associated with resource allocation by using multiple arbiters

Data transfer method

Memory system with calibrated data communication

Method and apparatus for multi-PHY communication without an ATM bus master

Bounded starvation checking of an arbiter using formal verification

Multiphase clocking systems with ring bus architecture

System and dynamic random access memory device having a receiver

One or more multiport systems to facilitate servicing of asynchronous communications events

Data processing unit and bus arbitration unit

Starvation prevention scheme for a fixed priority PCE-express arbiter with grant counters using arbitration pools

Semiconductor device

Semiconductor integrated circuit

Structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization

Method of piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization

SYSTEM ON CHIP DEVICE AND METHOD FOR MULTIPLE DEVICE ACCESS THROUGH A SHARED INTERFACE

Communication steering for use in a multi-master shared resource system

BUS ARBITRATION DEVICE

Integrated circuit including a plurality of master circuits transmitting access requests to an external device and integrated circuit system including first and second interated circuits each including a plurality of master circuits transmitting access requests

Method and apparatus for granting processors access to a resource

Information processing apparatus

Pin multiplexing

DEVICE INFORMATION MANAGEMENT SYSTEMS AND METHODS

Image processing controller and image forming apparatus

Opportunistic granting arbitration scheme for fixed priority grant counter based arbiter

Bus system and method of burst cycle conversion

Resource arbiter

Method and system for bus arbitration

Data processing apparatus and method for performing multi-cycle arbitration

Data processing apparatus and method for arbitrating between messages routed over a communication channel

Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system

SEMICONDUCTOR CIRCUIT

Method and system for providing access arbitration for an integrated circuit in a wireless device

Non-blocking bus controller for a pipelined, variable latency, hierarchical bus with point-to-point first-in first-out ordering

Integrated circuit device and signaling method with phase control based on information in external memory device

METHOD AND APPARATUS TO ALLOW DYNAMIC VARIATION OF ORDERING ENFORCEMENT BETWEEN TRANSACTIONS IN A STRONGLY ORDERED COMPUTER INTERCONNECT

Method and apparatus for arbitrating access

Apparatus and method for chained arbitration of a plurality of inputs

Integrated circuit memory device and signaling method for adjusting drive strength based on topography of integrated circuit devices

Integrated circuit device and signaling method with topographic dependent equalization coefficient

Arbiter circuit

Arbiter, crossbar, request selection method and information processing device

Interconnect logic for a data processing apparatus

Bus Arbitrating Device and Bus Arbitrating Method

Data processing system

Bus arbitration system, medium, and method

Information processing apparatus and access control method capable of high-speed data access

Arbitration apparatus, method, and computer readable medium with dynamically adjustable priority scheme

Arbiter and arbitrating method

Data transfer control device arbitrating data transfer among a plurality of bus masters

Segmented interconnect for connecting multiple agents in a system

Power efficient wireless network detection

Method and system for stream burst data transfer

Method and system for n dimension arbitration algorithm—scalable to any number of end points

Data processing device

Arbitrator and its arbitration method

SYSTEM AND METHOD FOR BANDWIDTH SHARING IN BUSSES

SYSTEM AND METHOD FOR BANDWIDTH SHARING IN BUSSES

Integrated Circuit Device that Stores a Value Representative of an Equalization Co-Efficient Setting

Data processor with a built-in memory

DATA PROCESSOR WITH A BUILT-IN MEMORY

DATA PROCESSOR WITH A BUILT-IN MEMORY

Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes

System bus control apparatus, integrated circuit and data processing system

POWER MANAGEMENT DEVICE WITH COMMUNICATIONS CAPABILITY AND METHOD OF USE

NETWORKABLE ELECTRICAL POWER DISTRIBUTION PLUGSTRIP WITH CURRENT DISPLAY AND METHOD OF USE

ELECTRICAL POWER DISTRIBUTION PLUGSTRIP WITH CURRENT INFORMATION DISPLAY AND METHOD OF USE

Method and system for multi-processor arbitration

Bus arbitration circuit and bus arbitration method

Method of setting priority of devices connected to bus, and apparatus having a plurality of devices and arbiter

Common memory transfer control circuit and common memory transfer control system

Data transfer bus system connecting a plurality of bus masters

Panel layout for an integrated power distribution system

Selection line and serial control of remote operated devices in an integrated power distribution system

NETWORK REMOTE POWER MANAGEMENT OUTLET STRIP

Segmented interconnect for connecting multiple agents in a system

PCI arbiter

Bus control system and a method thereof

Control method and control circuit for bus system

Bus system and method of arbitrating the same

Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus

SYSTEM AND METHOD FOR GENERATING BUS REQUESTS IN ADVANCE BASED ON SPECULATION STATES

NETWORK REMOTE POWER MANAGEMENT OUTLET STRIP

Software programmable dynamic arbitration scheme

HIGH-SPEED STARVATION-FREE ARBITER SYSTEM, ROTATING-PRIORITY ARBITER, AND TWO-STAGE ARBITRATION METHOD

Device for arbitrating bus accesses and method for controlling same

On-chip inter-subsystem communication including concurrent data traffic routing

On-chip inter-subsystem communication

BUS ARBITER AND BUS ARBITRATING METHOD

Data transfer system and data transfer method

Bus arbitration method and semiconductor apparatus

Data processor with a built-in memory

Method and system for master devices accessing slave devices

Method and apparatus of reducing transfer latency in an SOC interconnect

Calibrated data communication system and method

Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools

Method and apparatus for improved performance for priority agent requests when symmetric agent bus parking is enabled

Method and apparatus for round robin resource arbitration with a fast request to grant response

Bus controller

Bus deadlock avoidance

Method and apparatus for connecting an additional processor to a bus with symmetric arbitration

Data processing device

Bus arbitration system that achieves power savings based on selective clock control

System and method for an arbiter rewind

Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes

Bus request control circuit

Multi-stage round robin arbitration system

Managing a shared resource

Security system with an intelligent DMA controller

Integrated circuit device that stores a value representative of an equalization co-efficient setting

Method of arbitration which allows requestors from multiple frequency domains

Transparent high-speed multistage arbitration system and method

Employing one or more multiport systems to facilitate servicing of asynchronous communications events

Bus arbitration apparatus and bus arbitration method

Bus utilization based on data transfers on the bus

Network power management system

Bus system with protocol conversion for arbitrating bus occupation and method thereof

Network power administration system

Data transfer apparatus and transfer control program

Method of arbitration for bus use request and system therefor

Hierarchized arbitration method

Bus communication system

Console chip and single memory bus system

Apparatus and method for topography dependent signaling

[SYSTEM FOR ACCESSING A PLURALITY OF DEVICES BY USING A SINGLE BUS AND CONTROL APPARATUS THEREIN]

Apparatus and method for assuming mastership of a bus

Method and apparatus for scheduling a resource to meet quality-of-service restrictions

Method for arbitrating access to a shared resource

Communication steering for use in a multi-master shared resource system

Method and apparatus for configuring an interconnect to implement arbitration

Peripheral component interconnect arbiter implementation with dynamic priority scheme

Method and apparatus of allocating minimum and maximum bandwidths on a bus-based communication system with redundant communication circuits

Methods, circuits, and computer program products for variable bus arbitration

I/O throughput by pre-termination arbitration

Instruction supply control unit and semiconductor device