190357 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
Sub-classes:INTEGRATED CIRCUIT, CHIP, AND ELECTRONIC DEVICE
#2AXI BUS STRUCTURE AND CHIP SYSTEM
#3RESERVATION MECHANIC FOR NODES WITH PHASE CONSTRAINTS
#4Directing control data between semiconductor packages
#5Hybrid control plane data link agent and protocol
#6Semiconductor systems
#7Method of scheduling system-on-chip including real-time shared interface
#8System on chip (SoC), mobile electronic device including the same, and method of operating the SoC
#9Main board slot power control circuit
#10System on chip (SoC), mobile electronic device including the same, and method of operating the SoC
#11Asynchronous start for timed functions
#12Inter-integrated circuit bus arbitration system capable of avoiding host conflict
#13APPARATUS AND METHOD FOR CROSS ENCLAVE INFORMATION CONTROL
#14Multi-format driver interface
#15Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
#16Method for assigning addresses to nodes of a bus system, and installation
#17Connection management
#18Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
#19System and method to blacklist equalization coefficients in a high-speed serial interface
#20I/O COMMAND ID COLLISION AVOIDANCE IN A MEMORY DEVICE
#21Method of scheduling system-on-chip including real-time shared interface
#22Participating station for a bus system and method for data transmission in a bus system
#23Information processing system, information processing method, and recording medium
#24Methods and apparatus for augmented bus numbering
#25Wafer-level package with at least one input/output port connected to at least one management bus
#26Supporting flow control mechanism of bus between semiconductor dies assembled in wafer-level package
#27Serial bus system with switching modules
#28System on chip (SoC), mobile electronic device including the same, and method of operating the SoC
#29Configurable peripheral componenent interconnect express (PCIe) controller
#30Numerical control system
#31Issuing requests to a fabric
#32Method and system for accessing data
#33Method of optimizing the width of transaction ID for an interconnecting bus
#34Hierarchical reconfigurable computer architecture
#35Method and apparatus for arbitration with multiple source paths
#36Proactive quality of service in multi-matrix system bus
#37Interconnect, bus system with interconnect and bus system operating method
#38Method and system for changing bus direction in memory systems
#39Processor-based system hybrid ring bus interconnects, and related devices, processor-based systems, and methods
#40Device and method for writing/reading a memory register shared by a plurality of peripherals
#41Limiting bandwidth for write transactions across networks of components in computer systems
#42Issuing requests to a fabric
#43Method for Assigning Addresses to Nodes of a Bus System, and Installation
#44Interconnect, bus system with interconnect and bus system operating method
#45On-chip interconnect method, system and corresponding computer program product
#46Hierarchical reconfigurable computer architecture
#47Processor, processing system, data sharing processing method, and integrated circuit for data sharing processing
#48Back-off timing mechanism in a digital signal processor
#49Method for assigning addresses to nodes of a bus system, and installation
#50Bus-based communication system
#51Common access ring system
#52Round-robin bus protocol
#53Computer system and data pre-fetching method
#54Pipeline processing communicating adjacent stages and controls to prevent the address information from being overwritten
#55Method for changing ownership of a bus between master/slave devices
#56Multi-channel serial advanced technology attachment control system and control card thereof
#57Round-robin bus protocol
#58Data processing system with bus access retraction
#59Switch for distributed arbitration digital data buses
#60Fast arbitration scheme for a bus
#61Decentralized file system and message bus architecture for processing training sets in multi-cloud computing environment