190359 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
SYNCHRONOUS WIRED-OR ACK STATUS FOR MEMORY WITH VARIABLE WRITE LATENCY
#2SEMICONDUCTOR DEVICE, BUS CONTROL CIRCUIT AND BUS CONTROL METHOD
#3Arbitration allocating requests during backpressure
#4Digital signal processing circuit and corresponding method of operation
#5Information processing device for preventing occurrence of memory contention
#6Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling
#7Synchronous wired-or ACK status for memory with variable write latency
#8Digital signal processing circuit and corresponding method of operation
#9Secure timer synchronization between function block and external SOC
#10Data processing apparatus and operating method thereof
#11Data bus driver with electrical energy dump
#12Data processor including relay circuits coupled through a ring bus and method for controlling the same
#13Interrupt control apparatus, interrupt control method, and computer readable medium
#14System for online cascaded loading firmware based on boundary scan and method thereof
#15Data processor using a ring bus and method for controlling the same
#16All-connected by virtual wires network of data processing nodes
#17Synchronous wired-OR ACK status for memory with variable write latency
#18Self-configuring peripheral module
#19Systems and methods for providing communications with an improved network frame structure architecture within wireless sensor networks
#20Data bus driver with electrical energy dump
#21Data processor using a ring bus and method for controlling the same
#22Method, Apparatus, and System for Accessing Memory Device
#23Prioritizing I/O operations
#24SEMICONDUCTOR DEVICE
#25Systems and methods for providing communications with an improved network frame structure architecture within wireless sensor networks
#26DATA STORAGE DEVICE AND A METHOD FOR CONTROLLING ACCESS TO A MEMORY DEVICE OF A DATA STORAGE DEVICE
#27Register partition and protection for virtualized processing device
#28Devices and methods for prioritizing transmission of events on serial communication links
#29Data storage device and operating method thereof
#30Networked device connection management
#31Optimized credit return mechanism for packet sends
#32Optimized credit return mechanism for packet sends
#33All-connected by virtual wires network of data processing nodes
#34System and method for preventing time out in input/output systems
#35Synchronous wired-OR ACK status for memory with variable write latency
#36Multi-device synchronization of devices
#37Method and apparatus for preventing bank conflict in memory
#38System and method of a shared memory hash table with notifications and reduced memory utilization
#39Semiconductor device
#40Shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY)
#41Subscriber station for a bus system and method for time-optimized data transmission in a bus system
#42System, process control method and medium
#43Interface module
#44Computing architecture with peripherals
#45Arbitration in an SRIOV environment
#46Arbitration in an SRIOV environment
#47Storage module and method for determining ready/busy status of a plurality of memory dies
#48Intercomponent data communication
#49Intercomponent data communication
#50Intercomponent data communication between multiple time zones
#51Intercomponent data communication between different processors
#52PLC system having a plurality of CPU modules and control method thereof
#53Oldest link first arbitration between links grouped as single arbitration elements
#54Oldest link first arbitration between links grouped as single arbitration elements
#55Data processing device
#56Data transmission method for improving DMA and data transmission efficiency based on priorities of at least two arbitration units for each DMA channel
#57Clockless serial slave device
#58Bus auto-addressing system
#59Data transfer control apparatus
#60DISPLAY DEVICE
#61Maintaining I/O priority and I/O sorting
#62Apparatus and method for controlling execution of processes in a parallel computing system
#63Facilitating resource use in multicyle arbitration for single cycle data transfer
#64Facilitating resource use in multicycle arbitration for single cycle data transfer
#65Circuit for using shared memory, and method of storing determination result of arbitration content of arbitrator of this circuit
#66RECEPTION APPARATUS, INFORMATION PROCESSING APPARATUS AND METHOD OF RECEIVING DATA
#67Method for operating a bus system for communication with a plurality of communication nodes, and motor vehicle
#68Priority based connection arbitration in a SAS topology to facilitate quality of service (QoS) in SAS transport
#69Controlling bus access priority in a real-time computer system
#70Controlling bus access in a real-time computer system
#71Memory buffering system that improves read/write performance and provides low latency for mobile systems
#72Method and system for changing bus direction in memory systems
#73CAN bus edge timing control for dominant-to-recessive transitions
#74SAS EXPANDER
#75Scheduled peripheral component interconnect arbiter
#76Controller configured to control timing of access request according to density of burst access and access load
#77Controller using intermittent information
#78Device and method for global time information in event-controlled bus communication
#79Bus arbitration for a real-time computer system
#80Method and system for efficiently organizing data in memory
#81Dynamic data channel scheduling
#82Display controller driver and testing method thereof
#83Packet communication device for communicating packet to be transferred through packet communication which is time-managed in constant cycle and packet communication method thereof
#84Apparatus and method for controlling issuing of transaction requests
#85System, apparatus and method for granting access to a shared communications bus
#86Packet communication device for communicating packet to be transferred through packet communication which is time-managed in constant cycle and packet communication method thereof
#87Data accessing system and data accessing method
#88Memory buffering system that improves read/write performance and provides low latency for mobile systems
#89Method and device for exchanging data between at least two stations connected to a bus system
#90Memory controller, bus system, integrated circuit, and control method of integrated circuit including controlling flow of data to and from memory
#91Balancing PCI-express bandwidth
#92BUS SYSTEM AND CONTROL METHOD THEREOF
#93Method and system for efficiently organizing data in memory
#94Method and an Arrangement for Arbitrating Requests to Grant Access to Shared Resources
#95Variable time division multiplex transmission system
#96Method of designating slots in a transmission frame for controlling transmission of data over an interconnect coupling a plurality of master units with a plurality of slave units
#97Multi-master interconnect arbitration with time division priority circulation and programmable bandwidth/latency allocation
#98Time-based weighted round robin arbiter
#99Arrangement, device and method for controlling bus request signal generation
#100Method and apparatus for managing device reservation
#101Write reordering in a multiprocessor system
#102Reserving space in a mail queue
#103Synchronization mechanisms for high-integrity computing
#104Leases in a heterogenous data environment
#105Multi-core device with multi-bank memory
#106Cache contention management on a multicore processor based on the degree of contention exceeding a threshold