190369 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Information transfer, e.g. on bus; Bus structure; Coupling between buses with data restructuring
Sub-classes:Tunneling of Peripheral-Bus Protocol Traffic over Coherent Fabric and Chip-to-Chip or Die-to-Die Bus
#2Data synchronization method and apparatus, and device and storage medium
#3Communication device, communication system, and communication method
#4Non-transparent bridge selection
#5METHOD AND APPARATUS FOR PERFORMING ADDRESS TRANSLATIONS USING A REMAPPING PROCESS
#6CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY
#7Method and apparatus for supporting TCM communication by BIOS of ARM server, device, and medium
#8UNIDIRECTIONAL COMMAND BUS PHASE DRIFT COMPENSATION
#9Computational memory with zero disable and error detection
#10System and method for supporting chassis level keep alive in NVMe-oF based system
#11Communication device, communication system, and communication method for transmitting a serial signal group conforming to a serial peripheral interface
#12Multi-chip system and data transmission method thereof
#13Computing device processing expanded data
#14Computational memory with zero disable and error detection
#15Asymmetric high-speed interconnect routing interposer
#16Communicating non-isochronous data over an isochronous channel
#17Information Processing System And Computer-Readable Recording Medium Storing Program
#18Reducing coupling and power noise on PAM-4 I/O interface
#19Direct drive LED driver and offline charge pump and method therefor
#20Direct drive LED driver and offline charge pump and method therefor
#21System and method for supporting chassis level keep alive in NVME-of based system
#22Method and system for communicating over a bus
#23Low latency interconnect protocol for coherent multi-chip communication
#24Direct drive LED driver and offline charge pump and method therefor
#25Semiconductor memory device
#26Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator
#27Direct drive LED driver and offline charge pump and method therefor
#28Direct drive LED driver and offline charge pump and method therefor
#29Direct drive LED driver and offline charge pump and method therefor
#30Direct drive LED driver and offline charge pump and method therefor
#31Enabling arrangement for an electronic device with housing-integrated functionalities and method therefor
#32PCIe VIRTUAL SWITCHES AND AN OPERATING METHOD THEREOF
#33Self-tune controller
#34Data processing device, data processing system and method
#35Direct drive LED driver and offline charge pump and method therefor
#36Data processing device, data processing system and method
#37Extended fast memory access in a multiprocessor computer system
#38Zero-latency network on chip (NoC)
#39DDR4-SSD dual-port DIMM device
#40RDMA-SSD dual-port unified memory and network controller
#41System and method for communication between a data-acquisition circuit and a data-processing circuit
#42Cell library and method for designing an asynchronous integrated circuit
#43Technique for scaling the bandwidth of a processing element to match the bandwidth of an interconnect
#44Technique for scaling the bandwidth of a processing element to match the bandwidth of an interconnect
#45Enabling arrangement for an electronic device with housing-integrated functionalities and method therefor
#46Operating M-PHY based communications over serial advanced technology attachment (SATA)-based interface, and related cables, connectors, systems and methods
#47Bridge between two different controllers for transferring data between host and storage device
#48Universal digital block interconnection and channel routing
#49Data interface alignment
#50Information processing apparatus and control method thereof
#51Method, device, and system for packet transmission on PCIE bus
#52Universal serial bus (USB) to digital video
#53Method and system for hardware based implementation of USB 1.1 over a high speed link
#54Method and system for hardware based implementation of USB 1.1 over a high speed link
#55USB-to-SATA high-speed bridge
#56Implementing lane shuffle for fault-tolerant communication links
#57Apparatus and method for direct memory access in a hub-based memory system
#58Universal digital block interconnection and channel routing
#59Memory module and method for exchanging data in memory module
#60Zero-latency network on chip (NoC)
#61Universal serial bus (USB) to digital video
#62Universal serial bus (USB) to digital video
#63Extended fast memory access in a multiprocessor computer system
#64Methods for main memory with non-volatile type memory modules
#65Apparatus and method for direct memory access in a hub-based memory system
#66Multi-channel communication circuit
#67SAS reference Phys for virtualization and traffic isolation
#68Radio frequency module
#69Universal digital block interconnection and channel routing
#70Communication module system having an interface module and interface module
#71Methods for main memory with non-volatile type memory modules, and related technologies
#72Method and apparatus for implementing control of a multiple ring hybrid crossbar partially non-blocking data switch
#73Method and system for hardware based implementation of USB 1.1 over a high speed link
#74Back-off timing mechanism
#75Method and apparatus for network management system
#76Storage device flow control
#77Bus switch circuit and bus switch system
#78Methods and apparatuses to effect a variable-width link
#79Technique for lane virtualization
#80Apparatus and method for direct memory access in a hub-based memory system
#81Multi-host virtual bridge input-output resource switch
#82Method and apparatus for accessing a memory
#83Apparatus and method for direct memory access in a hub-based memory system
#84Interface conversion device of programmable logic controller (PLC) system and PLC system thereof
#85Asymmetric high-speed interconnect routing interposer
#86Circuits for and methods of asychronously transmitting data in an integrated circuit
#87Method and system for reducing the effect of component aging