190371 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Information transfer, e.g. on bus; Bus structure; Coupling between buses with data restructuring with data-width conversion
LOGICAL PHYSICAL LAYER INTERFACE SPECIFICATION SUPPORT FOR PCIE 6.0, CXL 3.0, AND UPI 3.0 PROTOCOLS
#2EXPANDED DATA LINK WIDTH FOR MAIN BAND CHIP MODULE CONNECTION IN ALTERNATE MODES
#3MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS
#4Computer Architecture Having Selectable Parallel and Serial Communication Channels Between Processors and Memory
#5Computer architecture having selectable parallel and serial communication channels between processors and memory
#6LINK WIDTH ADJUSTMENT METHOD AND APPARATUS
#7Multichip package with protocol-configurable data paths
#8Encoding byte information on a data bus with separate code
#9DATA TRANSMISSION METHOD AND DATA TRANSMISSION SYSTEM
#10Asymmetric read / write architecture for enhanced throughput and reduced latency
#11INFRASTRUCTURE INTEGRITY CHECKING
#12Method for data transmission and data-processing circuit
#13On-chip non-power of two data transactions
#14Integration of disparate system architectures using configurable isolated memory regions and trust domain conversion bridge
#15Sound processing method, sound device, and sound processing system
#16Multichip package with protocol-configurable data paths
#17Control method and control device of drive circuit and drive circuit
#18Infrastructure integrity checking
#19Asymmetric data communication for host-device interface
#20ASYNCHRONOUS TRANSCEIVER FOR ON-VEHICLE ELECTRONIC DEVICE
#21Signal channel switching method, display terminal and computer-readable storage medium
#22Protocol data unit end handling with fractional data alignment and arbitration fairness
#23Logical physical layer interface specification support for PCie 6.0, cxl 3.0, and UPI 3.0 protocols
#24Multichip package with protocol-configurable data paths
#25Convolutional neural network accelerating device and method with input data conversion
#26Asymmetric data communication for host-device interface
#27NFC and UWB communications
#28Data bit width converter and system on chip thereof
#29Data transmission using flippable cable
#30Support for multiple widths of DRAM in double data rate controllers or data buffers
#31Multichip package with protocol-configurable data paths
#32Queue manager for streaming multiprocessor systems
#33Asynchronous transceiver for on-vehicle electronic device
#34Simplified C-PHY high-speed reverse mode
#35Data transmission apparatus and data transmission method
#36Hardware independent peripheral control system and method
#37Queue manager for streaming multiprocessor systems
#38Double data rate controllers and data buffers with support for multiple data widths of DRAM
#39Systems, apparatus and methods for managing connectivity of networked devices
#40Bit manipulation capable direct memory access
#41Dynamic adaptation of direct memory transfer in a data processing system with mismatched data-bus widths
#42Integration of disparate system architectures using configurable isolated memory regions and trust domain conversion bridge
#43Computer architecture having selectable, parallel and serial communication channels between processors and memory
#44Memory systems and methods for dividing physical memory locations into temporal memory locations
#45Data bus logger
#46Asynchronous transceiver for on-vehicle electronic device
#47Computing device within memory processing and narrow data ports
#48DRAM data path sharing via a split local data bus
#49Low energy accelerator processor architecture
#50Configurable on-chip interconnection system and method and apparatus for implementing same, and storage medium
#51Non-volatile memory system with wide I/O memory die
#52Frame format for a serial interface
#53Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module
#54Microcontroller with variable length move instructions using direct immediate addressing or indirect register offset addressing
#55INFORMATION TRANSMISSION APPARATUS AND INFORMATION TRANSMISSION METHOD
#56Read delivery for memory subsystem with narrow bandwidth repeater channel
#57Systems and methods for thermal management of an information handling system including cooling for third-party information handling resource
#58Systems and methods for thermal management of an information handling system including determination of optimum slot location for information handling resource
#59Serial communication link with optimal transfer latency
#60Protocol conversion system
#61System and method for managing cache space and electronic device employing same
#62Asynchronous transceiver for on-vehicle electronic device
#63DRAM data path sharing via a split local data bus
#64Dynamic clock lane assignment for increased performance and security
#65Memory access unit for providing access to an item from an arbitrary location in physical memory
#66Dynamic link width modulation
#67Signal conditioner for high-speed data communications
#68Semiconductor device
#69Low energy accelerator processor architecture with short parallel instruction word and non-orthogonal register data file
#70Electronic device with card interface
#71Fault tolerant link width maximization in a data bus
#72Data transfer
#73MEMORY COMPONENT CAPABLE TO COMMUNICATE AT MULTIPLE DATA WIDTHS
#74SYSTEM AND METHOD FOR BUS WIDTH CONVERSION IN A SYSTEM ON A CHIP
#75SEMICONDUCTOR MEMORY CARD, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR MEMORY SYSTEM
#76Mode switching for increased off-chip bandwidth
#77ALLOCATING LANES OF A SERIAL COMPUTER EXPANSION BUS AMONG INSTALLED DEVICES
#78ALLOCATING LANES OF A SERIAL COMPUTER EXPANSION BUS AMONG INSTALLED DEVICES
#79Computer architecture having selectable, parallel and serial communication channels between processors and memory
#80Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module
#81Systems and methods for frequency control on a bus through superposition
#82Utilization-aware low-overhead link-width modulation for power reduction in interconnects
#83Start of sequence detection for one wire bus
#84System and method for conserving memory power using dynamic memory I/O resizing
#85Memory device formed with a semiconductor interposer
#86Synchronous Bus Width Adaptation
#87Bridge circuitry for communications with dynamically reconfigurable circuits
#88Memory systems and methods for dividing physical memory locations into temporal memory locations
#89Memory hub architecture having programmable lane widths
#90DATA PROCESSING APPARATUS AND CONTROL METHOD
#91Self correction logic for serial-to-parallel converters
#92Methods and systems to accomplish variable width data input
#93Memory access control module and associated methods
#94Circuit systems and methods using prime number interleave optimization for byte lane to time slice conversion
#95PCI express device and link energy management method and device
#96Utilization-aware low-overhead link-width modulation for power reduction in interconnects
#97Dynamic link width modulation
#98Versatile lane configuration using a PCIe PIe-8 interface
#99Versatile lane configuration using a PCIe PIE-8 interface
#100Method of data transmission in a system on chip
#101Cable with fade and hot plug features
#102Cable with video processing capability
#103High speed memory chip module and electronics system device with a high speed memory chip module
#104Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module
#105Representation of data relative to varying thresholds
#106Methods and systems to accomplish variable width data input
#107Embedded system capable of decreasing interrupt frequency of arm processor thereof
#108Programmable memory system
#109Memory systems and methods for dividing physical memory locations into temporal memory locations
#110Memory hub architecture having programmable lane widths
#111Electronic device with card interface
#112Methods and systems to accomplish variable width data input
#113SEMICONDUCTOR MEMORY CARD, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR MEMORY SYSTEM
#114APPARATUS AND METHOD FOR MULTIPLE ENDIAN MODE BUS MATCHING
#115Data generator providing large amounts of data of arbitrary word length
#116Control apparatus for fast inter processing unit data exchange in an architecture with processing units of different bandwidth connection to a pipelined ring bus
#117Integrated circuit system, and data readout method
#118Data transfer circuit
#119Electronic device with card interface
#120Adaptor for memory card
#121APPARATUS AND METHOD FOR WRITING BITWISE DATA IN SYSTEM ON CHIP
#122Methods and systems to accomplish variable width data input
#123Memory systems and methods for translating memory addresses to temporal addresses in support of varying data widths
#124Memory hub architecture having programmable lane widths
#125Lane merging
#126Information processing apparatus, information processing method and storage system
#127Data processing device adaptable to variable external memory size and endianess
#128SEMICONDUCTOR MEMORY CARD, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR MEMORY SYSTEM
#129Data input-output control apparatus
#130Method and system of supporting multi-plugging in X8 and X16 PCI express slots
#131Latency dependent data bus transmission
#132Serialization of data for communication with master in multi-chip bus implementation
#133Electronic device with card interface
#134Content data storage device and its control method
#135Memory hub architecture having programmable lane widths
#136Method and apparatus for updating wide storage array over a narrow bus
#137Bus width configuration circuit, display device, and method configuring bus width
#138Integrated circuit device and signal transmission system
#139Semiconductor device and BUS connecting method
#140Data transmission coordinating method
#141Method and system for transferring packets between devices connected to a PCI-Express bus
#142Method and System for Facilitating Faster Data Transmission between a Central Processing Unit and a Connected Memory Device
#143Semiconductor device to select and output data to a data bus
#144System and method of resizing PCI Express bus widths on-demand
#145Bus width automatic adjusting method and system
#146Word reordering upon bus size resizing to reduce Hamming distance
#147Electronic device with card interface
#148Bus controller for handling split transactions
#149Method and system of supporting multi-plugging in X8 and X16 PCI express slots
#150Integrated circuit device and signal transmission system
#151Data-width translator coupled between variable-width and fixed-width data ports and supporting multiple data-width configurations
#152System and method for measuring and correcting data lane skews
#153Lane merging
#154Performing an N-bit write access to an M×N-bit-only peripheral
#155Serial-to-parallel conversion/parallel-to-serial conversion/ FIFO unified circuit
#156Electronic device with card interface
#157Electronic device with card interface
#158Microprocessor apparatus and method for enabling variable width data transfers
#159Semiconductor integrated circuit
#160Interface circuit, system, and method for interfacing between buses of different widths
#161Efficient muxing scheme to allow for bypass and array access
#162Method for data communication
#163Architecture for accessing an external memory
#164Data generator for generating data of arbitrary length
#165Enhanced multi-access data port
#166Electronic device with card interface
#167Memory controller which increases bus bandwidth, data transmission method using the same, and computer system having the same
#168Methods and apparatuses to effect a variable-width link
#169Technique for lane virtualization
#170Interface integrated circuit device for a USB connection
#171Memory hub architecture having programmable lane widths
#172Various methods and apparatuses for width and burst conversion
#173Semiconductor integrated circuit having changeable bus width of external data signal
#174Electronic device with card interface
#175Integrated circuit with a scalable high-bandwidth architecture
#176Fragment storage for data alignment and merger
#177Data transfer control device and electronic instrument
#178Multi-port SRAM system for a distributed memory pool
#179Asymmetric read / write architecture for enhanced throughput and reduced latency
#180System and method of configuring information handling systems
#181Programmable data width converter device, system and method thereof
#182Scalable circuitry and method for control insertion
#183Multichip package with protocol-configurable data paths