Support of Option-ROM in socket-direct network adapters

USB hub

CONVERTING A STALE CACHE MEMORY UNIQUE REQUEST TO A READ UNIQUE SNOOP RESPONSE IN A MULTIPLE (MULTI-) CENTRAL PROCESSING UNIT (CPU) PROCESSOR TO REDUCE LATENCY ASSOCIATED WITH REISSUING THE STALE UNIQUE REQUEST

Clock synchronization apparatus and method

BUFFERING TRANSACTION REQUESTS TO A SUBSYSTEM VIA A BUS INTERCONNECT

Scalable input/output system and techniques to transmit data between domains without a central processor

Time-division-multiplexing of different protocols over a channel of an interface bus between die

Flex bus protocol negotiation and enabling sequence

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM

Bridging circuit and control system for automatic control of fluid dispensers, article dispensers, and related systems

Inter-die communication of programmable logic devices

Input/output hub

AIRCRAFT

Micro-architectural techniques to minimize companion die firmware loading times in a server platform

Apparatuses, methods, and systems for operations in a configurable spatial accelerator

Systems and methods for interconnecting GPU accelerated compute nodes of an information handling system

Timer control for peripheral component interconnect express components implemented with thunderbolt controllers

Method, apparatus and system for device transparent grouping of devices on a bus

GLOBALLY ADDRESSABLE MEMORY FOR DEVICES LINKED TO HOSTS

Technologies for application-specific network acceleration with unified coherency domain

Router-based transaction routing for toggle reduction

Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link

Accelerator interconnect assignments for virtual environments

Electronic device for recovering from buffer overrun in a bus system

FLASH-DRAM HYBRID MEMORY MODULE

Bridge and asynchronous channel based bus to provide UI-to-UI asynchronous communication

I2C device extender for inter-board communication over a single-channel bidirectional link

Asynchronous channel based bus architecture enabling decoupled services

INPUT/OUTPUT COMPUTER SYSTEM INCLUDING HARDWARE ASSISTED AUTOPURGE OF CACHE ENTRIES ASSOCIATED WITH PCI ADDRESS TRANSLATIONS

System and method for bus arrangement communications

Bus system and method for diagnosing a short circuit

System, apparatus and method for tunneling and/or multiplexing via a multi-drop interconnect

Computer system and a computer device

Controller to transmit data for components of a physical layer device

Programming interface operations in a port in communication with a driver for reinitialization of storage controller elements

Modular backplane

Universal ethernet solution

Microprocessor including a model of an enterprise

Apparatuses for providing data received by a state machine engine

Digital processing device with high connectivity and incoming/outgoing throughput embedded aboard a space platform and split up into mutually interconnected modular processing islets which are remote from one another on the scale of the platform

System and method to configure communication lanes of a central processing unit

Method and apparatus for controlling USB-C connectors on system with multiple host controllers

USB host-to-host auto-switching

Tunable bus-mediated coupling between remote qubits

Elevator data communication arrangement

Method for real time processing of fast analogue signals and a system for application thereof

Multiple security level monitor for monitoring a plurality of MIL-STD-1553 buses with multiple independent levels of security

System and method for extended peripheral component interconnect express fabrics

System and method for extended peripheral component interconnect express fabrics

Signal relaying device and signal relaying method

Graphics processing integrated circuit package

Method and device for universal serial bus (USB) communication

Device, apparatus and system to reduce current leakage during differential communications

METHOD AND APPARATUS FOR REDUCING WRITE CONGESTION IN NON-VOLATILE MEMORY BASED LAST LEVEL CACHES

Coupler for an automation system

Bus system and communication device

Extending multichip package link off package

Use of physical blocks to develop microservices

Receive queue with stride-based data scattering

Processing system with interspersed processors with multi-layer interconnection

Transmitter with independently adjustable voltage and impedance

Bus translator

Repetitive IO structure in a PHY for supporting C-PHY compatible standard and/or D-PHY compatible standard

Systems and methods for an error logging mechanism at controller area network buses

Data encoding using spare channels

Migrating virtual machines between compute systems by transmitting programmable logic accelerator state

Host configured multi serial interface device

Packet forwarding

Configuring NVMe devices for redundancy and scaling

INPUT/OUTPUT COMPUTER SYSTEM INCLUDING HARDWARE ASSISTED AUTOPURGE OF CACHE ENTRIES ASSOCIATED WITH PCI ADDRESS TRANSLATIONS

Delay control device, delay control method and electronic apparatus

Adjustment of buffer credits and other parameters in a startup phase of communications between a plurality of channels and a control unit

MODULAR COMMAND DEVICE FOR ELECTROVALVE ISLANDS

Programming interface operations in a driver in communication with a port for reinitialization of storage controller elements

Low power bidirectional bus

Stacking modular instrument system

Method and apparatus for data recovering during a board replacement

VALUE DOCUMENT HANDLING APPARATUS HAVING A DATA COMMUNICATION SYSTEM AND METHOD FOR DISTRIBUTING SENSOR DATA IN A VALUE DOCUMENT HANDLING APPARATUS

Server

Data processing device, data processing system and method

Interface for bridging out-of-band information from a downstream communication link to an upstream communication link

Misuse detection method, misuse detection electronic control unit, and misuse detection system

Communication device and control method

Information processing device, information processing method, and program

Memory system topologies including a buffer device and an integrated circuit memory device

Memory device with interleaved bank access

Farming data collection and exchange system

Link role determination in a dual-mode Peripheral Component Interconnect express (PCIe) device

USB PHY adapter IC with and circuit VBUS present output

Hot plug method, host controller, host, and PCIE bridge device

Game controller with structural bridge

Adjustments of buffer credits for optimizing the number of retry operations and transfer ready operations

Bridging between differing communication buses

Link-physical layer interface adapter

Memory module with timing-controlled data paths in distributed data buffers

Simultaneous inbound multi-packet processing

Computer system and a computer device

Receiving buffer credits by a plurality of channels of one or more host computational devices for transmitting data to a control unit

DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES

Firm channel paths

Integrated circuits having expandable processor memory

PCIe lane aggregation over a high speed link

Methods of automatically recording patching changes at passive patch panels and network equipment

UPDATED REGION COMPUTATION BY THE BUFFER PRODUCER TO OPTIMIZE BUFFER PROCESSING AT CONSUMER END

Implementing modal selection of bimodal coherent accelerator

Information processing apparatus, information processing method, and program

Method for determining a type of a device connected to an inter-integrated circuit (IC)

Switching device, peripheral component interconnect express system, and method for initializing peripheral component interconnect express system

Input-output module with multi-channel switching capability

Buffer device, an electronic system, and a method for operating a buffer device

Methods and systems for devices with self-selecting bus decoder

Communication system for controlling or monitoring vehicle components

Efficient low cost on-die configurable bridge controller

Implementing coherent accelerator function isolation for virtualization

Implementing coherent accelerator function isolation for virtualization

INTEGRATED CIRCUIT POWER DISTRIBUTION WITH THRESHOLD SWITCHES

Input/output computer system including hardware assisted autopurge of cache entries associated with PCI address translations

Virtual chassis management controller

Dragonfly processor interconnect network

Methods and apparatuses for providing data received by a state machine engine

Configuring wireless communications according to multiple communication protocols

Multi-level data cache and storage on a memory bus

System and method for memory access in server communications

Memory system and operation method of the same

Synchronous input/output computer system including hardware invalidation of synchronous input/output context

Multiple reset modes for a PCI host bridge

Integrated data concentrator for multi-sensor MEMS systems

Storage array including a bridge module interconnect to provide bridge connections to different protocol bridge protocol modules

Message translator

Communicating with machine to machine devices

Bridge board with structure for preventing solid state drive module bending and data storage device including the same

Processing system with interspersed processors with multi-layer interconnection

In-vehicle gateway device, storage control method, and computer program product

Method of handling transactions, corresponding system and computer program product

Reconfigurable test access port with finite state machine control

Universal serial bus data routing

Multiple input-output memory management units with fine grained device scopes for virtual machines

Time stamp conversion in an interface bridge

Remote host management over a network

Producer/consumer remote synchronization

Network interface card configuration method and resource management center

Coupling device and method for dynamically allocating USB endpoints of a USB interface, and exchange trading system terminal with coupling device

System-level interconnect ring for a programmable integrated circuit

Rail vehicle

Tunable bus-mediated coupling between remote qubits

Scalable input/output system and techniques to transmit data between domains without a central processor

Prevented inter-integrated circuit address conflict service system and method thereof

Proxy cache conditional allocation

Memory system topologies including a buffer device and an integrated circuit memory device

Precision time management (PTM) for USB retimers that accurately adjusts timestamp fields of isochronous timestamp packets (ITPS)

Solving unstable universal asynchronous receive transmit (UART) communication between a power manager and a universal serial bus (USB)-bridge device

Physical layer network interface module (PHY-NIM) adaptation system

DRAM data path sharing via a split local data bus and a segmented global data bus

Computer system

Multiprocessor system with improved secondary interconnection network

System and method for flexible storage and networking provisioning in large scalable processor installations

Integrated circuit with a serial interface

Dynamic Allocation of Computer Bus Lanes

Input/output switching method, electronic device, and system for a server

Configurable IO-channel system with embedded microcontroller

Communication low-speed and high-speed parallel bit streams over a high-speed serial bus

Systems and methods of in-situ digital eye characterization for serial data transmitter circuitry

ASIC chip system dedicated for optical three-dimensional sensing

Multiple reset modes for a PCI host bridge

Multiple reset modes for a PCI host bridge

REBOOT SYSTEM AND METHOD FOR BASEBOARD MANAGEMENT CONTROLLER

Metering accelerator usage in a computing system

Memory device having bank interleaving access

High performance interconnect link state transitions

Motherboard and computer control system including the same

Interface for memory readout from a memory component in the event of fault

Bus for communication between devices

Bridging between differing communication buses

Interconnect sharing with integrated control for reduced pinout

Programming interface operations in a port in communication with a driver for reinitialization of storage controller elements

Programming interface operations in a driver in communication with a port for reinitialization of storage controller elements

Avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols

Devices and methods for a data storage device

Processor with frames/bins structure in local high speed memory

Systems and methods for offloading link aggregation to a host bus adapter (HBA) in single root I/O virtualization (SRIOV) mode

COMMUNICATION DEVICE, COMMUNICATION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

UNIFIED SYSTEMS AND METHODS FOR INTERCHIP AND INTRACHIP NODE COMMUNICATION

Method, device, system and storage medium for implementing packet transmission in PCIE switching network

Microcontroller architecture with access stealing

Message passing framework for audio/video streaming in a topology of devices

Scaled PCI express credits

Storage system including a plurality of storage devices arranged in a holder

Thunderbolt sharing console and switching method thereof

Information processing apparatus and method of transferring data

Storage system bandwidth adjustment

Data processing device, data processing system and method

System and method for providing internal system interface-based bridging support in management controller

Computer system and a computer device

Field programmable gate array and communication method

Multi-processor startup system

Systems and methods to reprogram mobile devices

Apparatus and method for clock synchronization for inter-die synchronized data transfer

Computing system control

Interconnect to communicate information uni-directionally

Dynamic link width modulation

Methods and apparatuses for providing data received by a plurality of state machine engines

Single SDIO interface with multiple SDIO units

Input circuit that can be made redundant, input circuit unit having at least one input circuit, and method for operating the input circuit unit

Single relay SDIO interface with multiple SDIO units

Communication of device presence between boot routine and operating system

Control server system with a switch and comparing circuit for controlling a trigger time for buffer and power signal based on current status

Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link

System-level redundancy in PCI express equipment

Interface for a communication device and related methods

Semiconductor device

Converter module

Receiving buffer credits by a plurality of channels of one or more host computational devices for transmitting data to a control unit

Adjustment of buffer credits and other parameters in a startup phase of communications between a plurality of channels and a control unit

Adjustments of buffer credits for optimizing the number of retry operations and transfer ready operations

COMPUTER DEVICE WITH A TOUCH CONTROLLER AND METHOD FOR UPDATING THE TOUCH CONTROLLER

Processing system with interspersed processors with multi-layer interconnection

Circuit, parallel computing device, computer system and computer readable storage medium

PCIe lane aggregation over a high speed link

Processing system with interspersed processors DMA-FIFO

RESTART SYSTEM AND MOTHERBOARD THEREOF

Clock/power-domain crossing circuit with asynchronous FIFO and independent transmitter and receiver sides

Storage apparatus, control apparatus and computer-readable recording medium having stored therein control program

Allocating virtual resources to root PCI bus

PHY IC ACA bridge, RIDB resistance, and VBUS voltage circuits

CONTROLLER AREA NETWORK BUS

Low power parallelization to multiple output bus widths

Adapter board system

EXECUTION METHOD OF A STORAGE DEVICE STACKING SYSTEM

Minimizing thermal impacts of local-access PCI devices

Quality of service for internal I/Os using internal flow mechanism

Methods and Apparatus for IO, Processing and Memory Bandwidth Optimization for Analytics Systems

Computer mounting multiple modules facilitating opening/expansion control process with connectors

System and method for creating snapshots in openflame environment

Two level QoS scheduling for latency and queue depth control

Energy reserve conservation for vehicle communication module

SYSTEM-ON-A-CHIP (SOC) INCLUDING HYBRID PROCESSOR CORES

Method, apparatus and system to implement secondary bus functionality via a reconfigurable virtual switch

Hub devices and methods for initializing hub device

FPGA based ATCA (Advanced Telecommunications Computing Architecture) platform

Low power bidirectional bus

Device, system and method for communication with heterogeneous physical layers

Methods and apparatus for augmented bus numbering

High-frequency signal observations in electronic systems

Universal I/O signal interposer system

Device and system for bridging electrical signals between SIM card and mobile device and providing service to mobile device

Virtual system device identification using GPU to host bridge mapping

Managing single-wire communications

Communicating with machine to machine devices

Communicating with a machine to machine device

Communicating with a machine to machine device

Communicating with a machine to machine device

Secure communication with a mobile device

Communicating with a device

Managing machine to machine devices

Methods and systems for communicating with an M2M device

Quantum key distribution terminal and system

Methods of automatically recording patching changes at passive patch panels and network equipment

Implementing modal selection of bimodal coherent accelerator

Implementing modal selection of bimodal coherent accelerator

MODULAR SIGNAL INTERFACE UNIT

Transmission system, transmission device, and data transmission method

Peripheral component interconnect express (PCIe) hosts adapted to support remote PCIe endpoints

Implementing health check for optical cable attached PCIE enclosure

System and method for a low emission network

Hybrid memory blade

Flash-DRAM hybrid memory module

Farewell reset and restart method for coexistence of legacy and next generation devices over a shared multi-mode bus

Opaque bridge for peripheral component interconnect express bus systems

Memory system topologies including a buffer device and an integrated circuit memory device

Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions

Data communications system and method of data transmission

High performance interconnect link state transitions

DEVICE TABLE IN SYSTEM MEMORY

System on a chip comprising reconfigurable resources for multiple compute sub-systems

Test logic for a serial interconnect

APPARATUS, COMPUTER, AND METHOD OF SUPPORTING USB STORAGE DEVICE TO HOT PLUG

Multiprocessor system with improved secondary interconnection network

Dual access memory mapped data structure memory

Electronic device and method for fabricating the same

ELECTRONIC DEVICE AND ELECTRONIC DEVICE ASSEMBLY

Array processor having a segmented bus system

Implementing health check for optical cable attached PCIE enclosure

Bridge for bus-powered peripheral device power management

Detecting and configuring of external IO enclosure

Configuring a communication interconnect for electronic devices

Field bus coupler for connecting input/output modules to a field bus, and method of operation for a field bus coupler

Connector for a computing assembly

Detecting and configuring of external IO enclosure

Network traffic processing

Network traffic processing

HUB MODULE WITH A SINGLE BRIDGE SHARED AMONG MULTIPLE CONNECTION PORTS TO SUPPORT ROLE REVERSAL

Universal ethernet solution

Data writing system and method for DMA

Apparatus and method for RDMA with commit ACKs

METHODS AND SYSTEMS FOR NOTICING COMPLETION OF READ REQUESTS IN SOLID STATE DRIVES

Facilitating device driver interactions

Information system capable of expanding drive and bus number allocation method of the information system

I/O module, setting device, and method of building process control system

Throttling integrated link

Reconfigurable Modular Computing Device