Data Storage Devices with Services to Manage File Storage Locations

SECURE MANAGEMENT OF DEVICE CONTROL INFORMATION IN CONFIDENTIAL COMPUTING ENVIRONMENTS

STARTUP CONTROL METHOD, APPARATUS AND DEVICE FOR PCI DEVICES IN ARM SERVER

INTERFACE, ELECTRONIC DEVICE, AND COMMUNICATION SYSTEM

COMMUNICATION METHOD AND SYSTEM FOR DISTRIBUTED HETEROGENEOUS ACCELERATION PLATFORM, DEVICE AND MEDIUM

FRAME PACKING USING STORED TEMPLATES

AUTOMATING PCIe 6.0 TX EQUALIZER CALIBRATION USING A MULTIVARIABLE APPROACH

NETWORK STORAGE METHOD, STORAGE SYSTEM, DATA PROCESSING UNIT, AND COMPUTER SYSTEM

POOLING VOLATILE MEMORY RESOURCES WITHIN A COMPUTING SYSTEM

REMOTE MEMORY BRIDGE AND METHOD FOR OPERATION

Apparatus and methods for managing outstanding transactions between one or more requesting units and a target unit

Synchronous/asynchronous network communications layer

CHANNEL DIRECTION MANAGEMENT FOR BUS INTERFACES

STORAGE-INTEGRATED MEMORY EXPANDER, COMPUTING SYSTEM BASED COMPUTE EXPRESS LINK, AND OPERATING METHOD THEREOF

DEVICES USING CHIPLET BASED STORAGE ARCHITECTURES

DRAGONFLY ROUTING WITH INCOMPLETE GROUP CONNECTIVITY

FAT TREE ADAPTIVE ROUTING

System and method for power management of devices connected to data processing systems

METHOD AND SYSTEM FOR FACILITATING LOSSY DROPPING AND ECN MARKING

PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICE AND OPERATING METHOD THEREOF

BILLBOARD FOR CONTEXT INFORMATION SHARING

DISAGGREGATED DIE WITH INPUT/OUTPUT (I/O) TILES

SYSTEMS AND METHODS FOR GRAPHICALLY PROGRAMMING AN APPLICATION WITH EXTERNAL INTEGRATED CIRCUITS

Non-transparent bridge selection

SCALING MIDPLANE BANDWIDTH BETWEEN STORAGE PROCESSORS VIA NETWORK DEVICES

SYSTEMS AND METHODS OF DISTRIBUTED PARITY CALCULATION OFFLOADING

PERIPHERAL COMPONENT INTERCONNECT EXPRESS OVER FABRIC NETWORKS

Apparatuses, systems, and methods for providing communication between memory cards and host devices

COMPOSABLE INFRASTRUCTURE ENABLED BY HETEROGENEOUS ARCHITECTURE, DELIVERED BY CXL BASED CACHED SWITCH SOC

Innovative interconnect design for package architecture to improve latency

Multiplexer for selectively connecting a single KVM connection to multiple central processing units

ID-based transaction routing for PCIe endpoint lending

MULTI-FUNCTION FLEXIBLE COMPUTATIONAL STORAGE DEVICE

PARTITIONING RESPONSIVE TO PROCESSORS HAVING A DISPARATE NUMBER OF CORES

Resiliency Schemes for Distributed Storage Systems

SYSTEM COMMUNICATION TECHNIQUE OVER PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS) LINK

PERIPHERAL COMPONENT INTERCONNECT BOARD PROGRAMMABLE LINK TRAINING AND STATUS STATE MACHINE AND STATE BRANCHING

Hot-Plug Events In A Pool Of Reconfigurable Data Flow Resources

Cross Address-Space Bridging

CONFIGURABLE MEMORY POOL SYSTEM

Data transfer assemblies for robotic devices

System for monitoring and controlling host selection for a multi-host capable PCI-E device

METHOD AND SYSTEM FOR USING SECURE REMOTE DIRECT MEMORY ACCESS (RDMA) SYSTEM

AUTOMATIC TEST EQUIPMENT ARCHITECTURE PROVIDING ODD SECTOR SIZE SUPPORT

Peer-to-peer communications among communication fabric coupled endpoint devices

Controller-Level Memory Repair

SYSTEM AND METHOD FOR FACILITATING EFFICIENT UTILIZATION OF AN OUTPUT BUFFER IN A NETWORK INTERFACE CONTROLLER (NIC)

System and method for facilitating self-managing reduction engines

PCIe device

Loading firmware onto an embedded controller (EC) integrated into a heterogeneous computing platform

Loading firmware onto an external embedded controller (EC) of a heterogeneous computing platform

PCI-E bus standard compliant multifunctional interface board

Authentication and information system for reusable surgical instruments

Data bus inversion circuit and semiconductor apparatus including the same

Connecting non-PCIe accelerators as PCIe devices

Device ID setting method and electronic device applying the device ID setting method

2-wire interface and reset method thereof

BARE METAL COMPUTER FOR BOOTING COPIES OF VM IMAGES ON MULTIPLE COMPUTING DEVICES USING A SMART NIC

INFORMATION HANDLING SYSTEM HIGH BANDWIDTH GPU HUB

Programmable user-defined peripheral-bus device implementation using data-plane accelerator (DPA)

Data processing unit with transparent root complex

Shared storage model for high availability within cloud environments

SYSTEMS AND METHODS FOR GRAPHICALLY PROGRAMMING AN APPLICATION WITH EXTERNAL INTEGRATED CIRCUITS

Scaling midplane bandwidth between storage processors via network devices

Secure Collaboration Between Processors And Processing Accelerators In Enclaves

Memory system and host device

SEMICONDUCTOR DEVICE AND LINK CONFIGURING METHOD

SYSTEM AND METHOD FOR FACILITATING EFFICIENT ADDRESS TRANSLATION IN A NETWORK INTERFACE CONTROLLER (NIC)

SYSTEM AND METHOD FOR FACILITATING EFFICIENT MESSAGE MATCHING IN A NETWORK INTERFACE CONTROLLER (NIC)

System and method for facilitating operation management in a network interface controller (NIC) for accelerators

SYSTEM AND METHOD FOR FACILITATING FINE-GRAIN FLOW CONTROL IN A NETWORK INTERFACE CONTROLLER (NIC)

DRIVER TO PROVIDE CONFIGURABLE ACCESSES TO A DEVICE

Combining peripheral component interface express partial store commands along cache line boundaries

SYSTEM AND METHOD FOR FACILITATING ON-DEMAND PAGING IN A NETWORK INTERFACE CONTROLLER (NIC)

Dynamic random access memory applied to an embedded display port

DYNAMIC SWITCHING OF DATA TRANSFERS BETWEEN SIDEBAND AND MAINBAND

Latency reduction for link speed switching in multiple lane data links

Node identification allocation in a multi-tile system with multiple derivatives

Power management for peripheral component interconnect

SYSTEM AND METHOD FOR FACILITATING EFFICIENT PACKET FORWARDING USING A MESSAGE STATE TABLE IN A NETWORK INTERFACE CONTROLLER (NIC)

System and method for ghost bridging

PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICE AND OPERATING METHOD THEREOF

ISOLATED EXECUTION MECHANISM FOR CROSS-PLATFORM HARDWARE MANAGEMENT AGENT

MEMORY SYSTEM AND POWER CONTROL CIRCUIT

MEMORY SYSTEM AND CONTROL METHOD

User-defined peripheral-bus device implementation

Transferring data to a memory device based on importance

Input-output voltage control for data communication interface

METHOD AND DEVICE FOR DETECTING A CONNECTION OF A CHIP TO A PRINTING DEVICE

CXL PERSISTENT MEMORY MODULE LINK TOPOLOGY

CONFIGURABLE MULTI-SENSOR INPUT

SECURED PERIPHERAL DEVICE COMMUNICATION VIA BRIDGE DEVICE IN VIRTUALIZED COMPUTER SYSTEM

INPUT/OUTPUT EXPANSION EMULATION WITH A PROGRAMMABLE DEVICE

PAGE CACHE AND PREFETCH ENGINE FOR EXTERNAL MEMORY

SWITCH DEVICE FOR FACILITATING SWITCHING IN DATA-DRIVEN INTELLIGENT NETWORK

Resiliency schemes for distributed storage systems

SYSTEM WITH CACHE-COHERENT MEMORY AND SERVER-LINKING SWITCH

ALGORITHMS FOR USE OF LOAD INFORMATION FROM NEIGHBORING NODES IN ADAPTIVE ROUTING

Information processing apparatus, information processing system, connection control method, and non-transitory computer readable medium storing connection control program

Processor-endpoint isolation in communication switch coupled computing system

Content-Rich Error Notification

Exposing PCIE configuration spaces as ECAM compatible

METHOD FOR WRITING DATA FROM AXI BUS TO OPB AND METHOD FOR READING DATA FROM AXI BUS TO OPB BUS

Systems and methods for predictive signaling analytics in high-speed data links

Method for CXL fallback in a CXL system

Systems and methods for managing high-speed data links

Chip having dual-mode device that switches between root complex mode and endpoint mode in different system stages and associated computer system

STORAGE CONTROLLER AND STORAGE DEVICE COMPRISING THE SAME

Method for PCIe fallback in a CXL system

Transmit and receive circuits with multiple interfaces

High performance interconnect

MEMORY DISAGGREGATION METHOD, COMPUTING SYSTEM IMPLEMENTING THE METHOD

CXL memory expansion riser card

GRAPH ACCELERATION SOLUTION WITH CLOUD FPGA

Dynamic topology discovery and management with protocol detection

AUTOMATIC PROVISION OF HIGH SPEED SERIALIZER/DESERIALIZER LANES BY FIRMWARE

Peripheral component interconnect (PCI) hosting device

DATA TRANSMISSION METHOD, DEVICE, NETWORK SYSTEM, AND STORAGE MEDIUM

Dynamic allocation of peripheral component interconnect express bus numbers

SYSTEM AND METHOD OF DISAGGREGATED TIERED CACHE FOR CLOUD CONTENT STORAGE

System and method for facilitating efficient host memory access from a network interface controller (NIC)

System and method for facilitating data-driven intelligent network

Error correction

M.2 ADD-IN-CARD WITH UNIVERSAL FLASH STORAGE (UFS)

COMPOSABLE INFRASTRUCTURE ENABLED BY HETEROGENEOUS ARCHITECTURE, DELIVERED BY CXL BASED CACHED SWITCH SOC AND EXTENSIBLE VIA CXLOVERETHERNET (COE) PROTOCOLS

Synchronizing systems on a chip using a shared clock

Compute Express Link™ (CXL) Over Ethernet (COE)

Multi-port memory link expander to share data among hosts

System and method for a serial peripheral interface

PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME

Methods implementing doorbell register/file identification table with high-speed data communication fabric for cloud gaming data storage and retrieval

Memory system and computing system including the same

Method and system for providing network egress fairness between applications

DEVICES, SYSTEMS, AND METHODS FOR CONTROLLING COMMUNICATION BETWEEN APPARATUSES

Computing system including CXL switch, memory device and storage device and operating method thereof

Innovative interconnect design for package architecture to improve latency

Systems and methods involving hybrid quantum machines, aspects of quantum information technology and/or other features

Method and apparatus for configuring MMIOH base address of server system

MULTI-HOST NETWORKING SYSTEMS AND METHODS

Storage device, memory device, and system including storage device and memory device

Peripheral component interconnect express device and operating method thereof

TRUST DOMAINS FOR PERIPHERAL DEVICES

Initialization methods and associated controller, memory device and host

STREAMING FABRIC INTERFACE

STORAGE DEVICE AND COMPUTER DEVICE

Power management for peripheral component interconnect

Data transmission control device

Interface device and method of operating the same

PCI Express to PCI Express based Low Latency Interconnect Scheme for Clustering Systems

INTERFACE DEVICE AND COMPUTING SYSTEM INCLUDING THE SAME

Method, system, and server for monitoring status of solid state drive

Control of device features based on slot configurations

Interrupt emulation on network devices

Method, system, and apparatus for supporting multiple address spaces to facilitate data movement

CRYPTOGRAPHIC DATA INTEGRITY PROTECTION

Memory system

Memory system, method of controlling memory system, and host system

Message protocol for a data processing system

Dynamic virtual communication platform for healthcare

Controller, image forming apparatus, and access arbitration method

Autonomous entry and exit of low latency datapath in PCIe applications

Remote traffic performance on cluster-aware processors

Instant Submission Queue Release

CORRECTABLE ERROR TRACKING AND LINK RECOVERY

Method for dynamically modifying PCH PCIE root port where onboard VGA is located

Multichip system having command transfer mechanism and address generating method

CONTROL OF POWER USE OF A DEVICE POWERED BY A COMMUNICATION BUS AND DETERMINING SIDEBAND SIGNALING VOLTAGE LEVEL

Compute sled providing high speed storage access through a PCI express fabric between compute nodes and a storage server

Method to improve communication speed in existing control system

Multi-channel system architecture for managing flow of data and associated trace information

Flexible queue provisioning for partitioned acceleration device

Small cell millimeter wave and sub-6 GHz modules coexistence

LOGIC CONTROLS FOR GRAPHICS CARD AIR MOVING DEVICES

Receiver side setup and hold calibration

COORDINATING TIMER ACCESS FOR VIRTUAL MACHINES USING PERIPHERAL COMPONENT INTERFACE CARDS

Methods for preventing PCIe misconfigurations

Scalable storage using NVMe communication

Shadow DRAM with CRC+RAID architecture, system and method for high RAS feature in a CXL drive

Method and apparatus for establishing trusted PCIe resource sharing

VRAN with PCIe fronthaul

Trust domains for peripheral devices

Pushing a firmware update patch to a computing device via an out-of-band path

Distributed midplanes

PCIe peripheral sharing

Multiple port emulation

Resiliency schemes for distributed storage systems

Storage device, nonvolatile memory system including memory controller, and operating method of the storage device

PCIE device, apparatus, and method with different bandwidths compatible in same slot

Dual-access high-performance storage for BMC to host data sharing

ALLOCATING PERIPHERAL COMPONENT INTERFACE EXPRESS (PCIE) STREAMS IN A CONFIGURABLE MULTIPORT PCIE CONTROLLER

Multi-node memory address space for PCIe devices

Modular object-oriented digital sub-system architecture with primary sequence control and synchronization

Data distribution device, data distribution method and related computing system

Dual-mode sideband interface for smart network interface controller

CIRCUITRY AND METHODS FOR IMPLEMENTING INPUT/OUTPUT EXTENSIONS FOR TRUST DOMAINS

Hardware device for enforcing atomicity for memory operations

Disaggregated memory server having chassis with a plurality of receptacles accessible configured to convey data with PCIe bus and plurality of memory banks

Memory-flow control register

Memory request modulation

Retrieving diagnostic information from a PCI express endpoint

Peripheral component interconnect express device startup method and apparatus, and storage medium

Packet control apparatus and packet control method

Software or firmware managed hardware capability and control configuration for PCIe devices

Low-latency input data staging to execute kernels

Clock control method, apparatus, and device, and storage medium

Firmware retrieval and analysis

Embedded physical layers with passive interfacing for configurable integrated circuits

POWER-SAVING TECHNIQUES IN COMPUTING DEVICES THROUGH COMMUNICATION BUS CONTROL

Card reading device and electronic device with card reading function

PCIe communications

SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME

Enterprise host memory buffer

Control method, electronic device, and writing interaction device

Storage system

METHOD FOR EXPANDING PCIE SYSTEM, PCIE SWITCHING DEVICE, AND PCIE SYSTEM

Multiprocessor system and method for configuring multiprocessor system

Peer-to-peer communications initiated among communication fabric coupled endpoint devices

Peer-to-peer communications among communication fabric coupled endpoint devices

GENERIC APPROACH FOR VIRTUAL DEVICE HYBRID COMPOSITION

Method of automatic identification and protection of correct PCIe configuration of a server and server applying the method

NUMA node virtual machine provisioning system

Information handling system bus out of band message access control

Inter-baseboard management controller (BMC) integration for high performance computing platforms

Server network interface card-located baseboard management controllers

Storage system boot method and apparatus, and computer-readable storage medium

RESOURCE MANAGEMENT FOR DISAGGREGATED ARCHITECTURES

SYSTEM AND METHOD FOR VALIDATING A POWER CYCLE FOR AN EMULATED PCIe BASED STORAGE DEVICE

VIRTUALIZATION METHOD, DEVICE, BOARD CARD AND COMPUTER READABLE STORAGE MEDIUM

Controller and memory system

Intra-chassis device multi-management domain system

Synchronizing systems on a chip using a shared clock

HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES

SERDES circuit automatic gain control and convergence

RIGHT-ANGLED ORTHOGONAL CONNECTOR ASSEMBLY HAVING A WIRE TERMINATION TO A HIGH-SPEED CABLE

Storage device and system of controlling operation through flow control monitoring

FUZZING BASED SECURITY ASSESSMENT

Transaction analyzer for communication bus traffic

Shared storage model for high availability within cloud environments

SCALABLE ADDRESS DECODING SCHEME FOR CXL TYPE-2 DEVICES WITH PROGRAMMABLE INTERLEAVE GRANULARITY

DEVICES USING CHIPLET BASED STORAGE ARCHITECTURES

Secure and power efficient audio data processing

DEVICE VIRTUALIZATION TECHNIQUES

Data transmission method and electronic chip of the manycore type

IN-MEMORY COMPUTING WITH CACHE COHERENT PROTOCOL

Device ID setting method and electronic device applying the device ID setting method

Method and system for sequencing data checks in a packet

Managing inter-processor interrupts in virtualized computer systems

Anamoly detection system for peripheral component interconnect express

Methods for data bus inversion

System supporting virtualization of SR-IOV capable devices

Multi-function flexible computational storage device

DYNAMIC ALLOCATION OF SHARED BUS LANES

Method and system for facilitating lossy dropping and ECN marking

System supporting virtualization of SR-IOV capable devices

Conversion adapter and conversion adaptation method between PCIE and SPI realized based on FPGA

DATA COMMUNICATION BETWEEN A HOST COMPUTER AND AN FPGA

Transaction layer circuit of PCIe and operation method thereof

Power supply device, power supply system and non-transitory computer-readable recording medium

COMPOSABLE INFRASTRUCTURE ENABLED BY HETEROGENEOUS ARCHITECTURE, DELIVERED BY CXL BASED CACHED SWITCH SOC AND EXTENSIBLE VIA CXLOVERETHERNET (COE) PROTOCOLS

APPARATUSES AND METHODS

Extended memory architecture

System, method, and apparatus for SRIS mode selection for PCIE

TRANSACTIONAL MEMORY SUPPORT FOR COMPUTE EXPRESS LINK (CXL) DEVICES

DISAGGREGATED MEMORY SERVER

ALIAS MANAGEMENT METHOD AND DEVICE

Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC

Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC

Communications Method and Related Apparatus

High density peripheral card chassis

System and method for providing in-storage acceleration (ISA) in data storage devices

Determination of power-off duration of NVME SSD

Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC

Latency and jitter for traffic over PCIe

CHIP HAVING DUAL-MODE DEVICE THAT SWITCHES BETWEEN ROOT COMPLEX MODE AND ENDPOINT MODE IN DIFFERENT SYSTEM STAGES AND ASSOCIATED COMPUTER SYSTEM

Synchronous serial interface allowing communication with multiple peripheral devices using a single chip select

COMMUNICATION PROTOCOLS FOR SECURE DIGITAL (SD) CARDS

Managed NAND Flash memory region control against endurance hacking

PCIE-BASED COMMUNICATIONS METHOD AND APPARATUS

METHOD AND SYSTEM FOR DATA TRANSACTIONS ON A COMMUNICATIONS INTERFACE

System and method of interfacing co-processors and input/output devices via a main memory system

Transparent remote memory access over network protocol

Cross bus memory mapping

INFORMATION PROCESSING DEVICE, OPERATION CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING OPERATION CONTROL PROGRAM

Embedded computation instruction performance profiling

Peripheral component interconnect express interface device and operating method thereof

Peripheral component interconnect express device and operating method thereof

System with cache-coherent memory and server-linking switch

Billboard for context information sharing

Peripheral component interconnect express (PCIE) device for supporting separate reference clock(s) operating between host and direct memory access (DMA) controller

Peripheral component interconnect express interface device and operating method thereof

System and method for bypass memory read request detection

Acceleration circuitry for posit operations

Storage assisted virtual machine backups using storage VMOTION and XCOPY

Ultrasonic system and imaging ultrasonic method

Generic Packet Header Insertion and Removal

PCI Express to PCI Express based low latency interconnect scheme for clustering systems

PCIe data transmission method and apparatus

Peripheral component interconnect express device and computing system including the same

Peripheral component interconnect express device and operating method thereof

PCIe-Based Data Transmission Method and Apparatus