190397 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Information transfer, e.g. on bus; Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
Sub-classes:SOLID-STATE DRIVE HAVING SHARED WORK QUEUE FOR RECEIVING ACCESS COMMANDS
#2SYSTEMS AND METHODS FOR SEMICONDUCTOR DEVICES WITH EXTENDED HIGH-BANDWIDTH MEMORY (HBM) OFFSETS
#3RETAINING THE NON-VOLATILE MEMORY EXPRESS CACHED DATA DURING VIRTUAL MACHINE MIGRATION IN A CLOUD SETUP
#4SYSTEMS, METHODS, AND DEVICES FOR NEAR DATA PROCESSING
#5Memory Die Interconnections to Physical Layer Interfaces
#6MANAGEMENT COMPONENT TRANSPORT PROTOCOL
#7SYSTEM, METHOD AND APPARATUS FOR HYBRID MODE MEMORY HAVING FINE-GRAINED INTERLEAVING OF DISPARATE ADDRESS RANGES
#8APPARATUSES, SYSTEMS, AND METHODS FOR PROVIDING COMMUNICATION BETWEEN MEMORY CARDS AND HOST DEVICES
#9SYSTEM TO OPTIMIZE VIDEO STREAMING OF USB CAMERA VIA BULK ENDPOINT
#10Computing device having a non-volatile weight memory
#11COMMUNICATING DATA WITH STACKED MEMORY DIES
#12PACKET ROUTING BETWEEN MEMORY DEVICES AND RELATED APPARATUSES, METHODS, AND MEMORY SYSTEMS
#13SYSTEMS, METHODS, AND APPARATUS FOR UPSTREAM PORT DUPLICATION ON VIRTUAL SWITCHES
#14Method and Apparatus for Collaborative Memory Accesses
#15THERMAL MITIGATION FOR SOC USING MEMORY ACCESS LATENCY
#16MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP
#17MEMORY DEVICE AND HOST DEVICE
#18MEMORY SYSTEMS HAVING CONTROLLERS EMBEDDED IN PACKAGES OF INTEGRATED CIRCUIT MEMORY
#19Systems and Methods For High Bandwidth Memory With Unidirectional Data Flow
#20SERIAL INTERFACE FOR AN ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SUB-SYSTEM
#21DEVICE CONTROL METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
#22Memory Validation
#23MEMORY PROTOCOL
#24SYSTEMS AND METHODS FOR SEMICONDUCTOR DEVICES WITH EXTENDED HIGH-BANDWIDTH MEMORY (HBM) OFFSETS
#25Computer Architecture Having Selectable Parallel and Serial Communication Channels Between Processors and Memory
#26MEMORY SYSTEM WITH INDEPENDENTLY ADJUSTABLE CORE AND INTERFACE DATA RATES
#27AXI-TO-MEMORY IP PROTOCOL BRIDGE
#28PCIE CHANNEL SWITCHES IN DATA TRANSMISSION SYSTEMS
#29SYSTEM AND METHOD FOR PROVIDING IN-STORAGE ACCELERATION (ISA) IN DATA STORAGE DEVICES
#30Byte-addressable device and computing system including same
#31SYSTEMS, DEVICES AND METHODS WITH OFFLOAD PROCESSING DEVICES
#32PACKET ROUTING BETWEEN MEMORY DEVICES AND RELATED APPARATUSES, METHODS, AND MEMORY SYSTEMS
#33Apparatuses, systems, and methods for providing communication between memory cards and host devices
#34Memory Die Interconnections to Physical Layer Interfaces
#35Transmitting a response with a request and state information about the request
#36APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES FOR MULTI-LEVEL COMMUNICATION ARCHITECTURES
#37Peer-to-peer communications among communication fabric coupled endpoint devices
#38Processor for a cryptosystem
#39MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARYING PHYSICAL DIMENSIONS, MEMORY FORMATS, AND OPERATIONAL CAPABILITIES
#40Memory validation
#41MEMORY DEVICE WITH EMBEDDED DEEP LEARNING ACCELERATOR IN MULTI-CLIENT ENVIRONMENT
#42Computing system and associated method
#43SYSTEM AND METHOD FOR UTILIZING A DATA STORAGE DEVICE WITH POWER PERFORMANCE PROFILES AND/OR TEMPERATURE MONITORING
#44Memory system and method of controlling a memory chip
#45Coherency Domain Cacheline State Tracking
#46Communicating data with stacked memory dies
#47Computer architecture having selectable parallel and serial communication channels between processors and memory
#48SCALABLE 2.5D INTERFACE CIRCUITRY
#49Low-Pincount High-Bandwidth Memory And Memory Bus
#50SYSTEMS AND METHODS FOR SCALABLE AND COHERENT MEMORY DEVICES
#51Method and apparatus for configuring MMIOH base address of server system
#52Detection method and detection device for determining whether communication protocol is UART, I2C BUS, or SPI
#53STORAGE APPARATUS WITHOUT SINGLE FAILURE POINT
#54SYSTEMS, DEVICES AND METHODS WITH OFFLOAD PROCESSING DEVICES
#55APPARATUS FOR READ/WRITE OPERATIONS ON SAS HARD DISK THROUGH USB INTERFACE
#56Peer-to-peer communications initiated among communication fabric coupled endpoint devices
#57Peer-to-peer communications among communication fabric coupled endpoint devices
#58Memory device and host device
#59Method for transferring data on a memory card in synchronism with a rise edge and a fall edge of a clock signal
#60Serial interface for an active input/output expander of a memory sub-system
#61Asynchronous reservation of storage volumes with persistent storage of reservation data
#62System and method for providing in-storage acceleration (ISA) in data storage devices
#63Communicating data with stacked memory dies
#64System and method of interfacing co-processors and input/output devices via a main memory system
#65UNIDIRECTIONAL COMMAND BUS PHASE DRIFT COMPENSATION
#66Efficient retrieval of sensor data while ensuring atomicity
#67Memory with a communications bus for device-to-controller communication, and associated systems, devices, and methods
#68Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities
#69Memory system and data processing system
#70STORAGE SYSTEM, STORAGE DEVICE, AND OPERATION METHOD OF STORAGE DEVICE
#71Memory system with independently adjustable core and interface data rates
#72Apparatuses, systems, and methods for providing communication between memory cards and host devices
#73Methods and apparatus for data descriptors for high speed data systems
#74Signal transmitting circuit, and semiconductor apparatus and semiconductor system using the same
#75Techniques to support mulitple interconnect protocols for an interconnect
#76Memory system and method of controlling a memory chip
#77Directing communication of data from an image sensor
#78Memory protocol
#79Scalable 2.5D interface circuitry
#80Nonvolatile logic memory for computing module reconfiguration
#81Method for PRP/SGL handling for out-of-order NVME controllers
#82OFF-PACKAGE HIGH DENSITY, HIGH BANDWIDTH MEMORY ACCESS USING OPTICAL LINKS
#83High bandwidth controller memory buffer (CMB) for peer to peer data transfer
#84Packet routing between memory devices and related apparatuses, methods, and memory systems
#85Configuring multiple register clock drivers of a memory subsystem
#86PCIe device peer-to-peer communications
#87Data writing method and apparatus
#88Systems and methods for scalable and coherent memory devices
#89Efficient management of bus bandwidth for multiple drivers
#90Active-active architecture for distributed ISCSI target in hyper-converged storage
#91Multi-ported nonvolatile memory device with bank allocation and related systems and methods
#92SYSTEMS, METHODS, AND DEVICES FOR NEAR DATA PROCESSING
#93Method of accessing a memory, and corresponding circuit
#94Host device with automated connectivity provisioning
#95System and method of interfacing co-processors and input/output devices via a main memory system
#96Low-pincount high-bandwidth memory and memory bus
#97Multi-frequency memory interface and methods for configurating the same
#98System and method for optimizing DRAM bus switching using LLC
#99Host device with efficient automated seamless migration of logical storage devices across multiple access protocols
#100Storage device for storing model information, storage system including the storage device, and operating method of the storage system
#101Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures
#102Method for transferring data on a memory card in synchonism with a rise edge and a fall edge of a clock signal
#103MULTI-MODE NMVE OVER FABRICS DEVICES
#104HUB CIRCUIT FOR A DIMM HAVING MULTIPLE COMPONENTS THAT COMMUNICATE WITH A HOST
#105Memory device and host device
#106Methods and apparatus for DMA engine descriptors for high speed data systems
#107Apparatuses and methods for in-memory data switching networks
#108Techniques for reducing the overhead of providing responses in a computing network
#109Data processing system and operating method thereof
#110Multi-ported nonvolatile memory device with bank allocation and related systems and methods
#111Methods for error detection and correction and corresponding systems and devices for the same
#112Scalable 2.5D interface circuitry
#113System and method of interfacing co-processors and input/output devices via a main memory system
#114Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories
#115Hybrid hardware-software coherent framework
#116MEMORY CONTROL COMPONENT WITH INTER-RANK SKEW TOLERANCE
#117System and method for providing in-storage acceleration (ISA) in data storage devices
#118Memory system with independently adjustable core and interface data rates
#119Hybrid architecture for signal processing and signal processing accelerator
#120Multi-mode NMVe over fabrics devices
#121Memory card and host device thereof
#122Low-pincount high-bandwidth memory and memory bus
#123Programmable data bus inversion and configurable implementation
#124Active-active architecture for distributed ISCSI target in hyper-converged storage
#125PCIe device peer-to-peer communications
#126Memory controller for storage device, storage device, control method of storage device, and recording medium
#127Scalable 2.5D interface circuitry
#128Memory protocol
#129Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities
#130Method for controlling power supply in semiconductor device
#131Data transmission circuit for operating a data bus inversion, and a semiconductor apparatus and a semiconductor system including the same
#132Management of data written via a bus interface to a storage controller during consistent copying of data
#133Method for accessing extended memory, device, and system
#134Writes to multiple memory destinations
#135Nonvolatile logic memory for computing module reconfiguration
#136Multiple transaction data flow control unit for high-speed interconnect
#137Memory mirroring
#138Interface for memory having a cache and multiple independent arrays
#139Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines
#140Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories
#141Scalable 2.5D interface circuitry
#142Wide programmable gain receiver data path for single-ended memory interface application
#143Electronic device and data transmitting/receiving method
#144Memory module and data processing system for reducing heat generation
#145Apparatuses and methods for exiting low power states in memory devices
#146Memory channel that supports near memory and far memory access
#147Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures
#148Nucleic acid based data storage
#149Low-pincount high-bandwidth memory and memory bus
#150NETWORK-ON-CHIP AND COMPUTER SYSTEM INCLUDING THE SAME
#151Interface for memory having a cache and multiple independent arrays
#152Memory device and host device
#153Multi-mode NVMe over fabrics devices
#154Real-time input/output bandwidth estimation
#155DQS gating in a parallelizer of a memory device
#156Memory systems having controllers embedded in packages of integrated circuit memory
#157System and method of interfacing co-processors and input/output devices via a main memory system
#158Management of data written via a bus interface to a storage controller during consistent copying of data
#159Sidefiles for management of data written via a bus interface to a storage controller during consistent copying of data
#160Dynamic per-bank and all-bank refresh
#161Flash medium access method and controller
#162Multiple transaction data flow control unit for high-speed interconnect
#163Method and device for improved advanced microcontroller bus architecture (AMBA) and advanced extensible interface (AXI) operations
#164Three-dimensional stacked memory optimizations for latency and power
#165Memory component with multiple command/address sampling modes
#166Memory system for adjusting clock frequency
#167Performance Level Adjustments in Memory Devices
#168Power saving techniques for memory systems by consolidating data in data lanes of a memory bus
#169Semiconductor memory device for sharing inter-memory command and information, memory system including the same and method of operating the memory system
#170Hybrid architecture for signal processing and signal processing accelerator
#171Integrator for a storage device, corresponding storage device and method of manufacturing the same
#172Flash controller to provide a value that represents a parameter to a flash memory
#173System and method for early data pipeline lookup in large cache design
#174Network failover handling in computing systems
#175Semiconductor system
#176Method to reduce write responses to improve bandwidth and efficiency
#177Autonomous prefetch engine
#178I/O driven data transfer in a data processing network
#179Cache self-clean engine
#180Memory card and host device thereof
#181Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines
#182Network server systems, architectures, components and related methods
#183System and method for providing near storage compute using a bridge device
#184System and method for providing in-storage acceleration (ISA) in data storage devices
#185Communicating data with stacked memory dies
#186Active extensible memory hub
#187Data transmission circuit with encoding circuit, and semiconductor apparatus and semiconductor system including the data transmission circuit
#188System and method for channel time management in solid state memory drives
#189Medical device connectivity interface system and method
#190Clock tree structure in a memory system
#191Host controller apparatus, host controller device, and method for a host controller for determining information related to a time shift for transmitting instructions on a command and address bus, host controller and computer system
#192Hub circuit for a DIMM having multiple components that communicate with a host
#193Scalable memory-optimized hardware for matrix-solve
#194Method, system, and device for near-memory processing with cores of a plurality of sizes
#195Computer architecture having selectable, parallel and serial communication channels between processors and memory
#196Masking the influence of unsupported fieldbus commands
#197Memory channel that supports near memory and far memory access
#198Interconnect systems and methods using memory links to send packetized data between different data handling devices of different memory domains
#199TECHNIQUES TO SUPPORT MULITPLE INTERCONNECT PROTOCOLS FOR AN INTERCONNECT
#200Memory controller
#201High bandwidth memory (HBM) bandwidth aggregation switch
#202Semiconductor system
#203Multi-channel DIMMs
#204Multi-Memory Collaboration Structure Based on SPI Interface
#205Multiple storage devices implemented using a common connector
#206Apparatuses and methods for in-memory data switching networks
#207Storage device, data processing system, and method for operating the storage device
#208Methods and apparatus for controlling interface circuitry
#209Devices and methods for autonomous hardware management of circular buffers
#210Memory device and host device
#211Memory channel that supports near memory and far memory access
#212Memory clock frequency adjusting method, mainboard, and computer operating system
#213RING NETWORK SYSTEM USING PERIPHERAL COMPONENT INTERCONNECT EXPRESS AND SETTING METHOD THEREOF
#214Parallel processing apparatus and inter-node communication method
#215Memory protocol
#216Semiconductor system
#217Memory control component with dynamic command/address signaling rate
#218Computer and quality of service control method and apparatus
#219Multiprocessor cache buffer management
#220Non-volatile memory system with wide I/O memory die
#221Nucleic acid based data storage
#222SCRATCHPAD MEMORY WITH BANK TILING FOR LOCALIZED AND RANDOM DATA ACCESS
#223Apparatus including a memory controller for controlling direct data transfer between first and second memory modules using direct transfer commands
#224Memory mirroring
#225Memory control circuit and memory controlling method
#226Memory card and host device thereof
#227Method for controlling power supply in semiconductor device
#228Optical transceiver and method of downloading data
#229Multi-mode NMVE over fabrics devices
#230Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module
#231Innovative high speed serial controller testing
#232Innovative high speed serial controller testing
#233Front end traffic handling in modular switched fabric based data storage systems
#234Low-pincount high-bandwidth memory and memory bus
#235Apparatuses and methods for exiting low power states in memory devices
#236Memory and method for operating a memory with interruptible command sequence
#237Termination schemes for multi-rank memory bus architectures
#238Memory system with independently adjustable core and interface data rates
#239Data bus driving circuit, and semiconductor device and semiconductor memory device including the same
#240Read training a memory controller
#241Failover handling in modular switched fabric for data storage systems
#242Power saving techniques for memory systems by consolidating data in data lanes of a memory bus
#243Memory channel that supports near memory and far memory access
#244Semiconductor device and data processing system with coordinated calibration and refresh operations
#245Architectures and methods for processing data in parallel using offload processing modules insertable into servers
#246Modular switched fabric for data storage systems
#247Non-volatile memory interface
#248Chained bus memory device
#249Apparatuses and methods for exiting low power states in memory devices
#250Semiconductor system
#251Logic-based decoder for crosstalk-harnessed signaling
#252Direct interface between graphics processing unit and data storage unit
#253Programmable input/output (PIO) engine interface architecture with direct memory access (DMA) for multi-tagging scheme for storage devices
#254Memory control component with inter-rank skew tolerance
#255Techniques for inter-component communication based on a state of a chip select pin
#256Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device
#257SYSTEM OF AT LEAST TWO MICROCONTROLLERS, AND METHOD FOR PRODUCING SUCH A SYSTEM
#258Nonvolatile logic memory for computing module reconfiguration
#259Handling CPU hotplug events in RCU without sleeplocks
#260Handling CPU hotplug events in RCU without sleeplocks
#261Leveraging multiprocessor fabric link aggregation
#262Deferred assignment of devices in virtual machine migration
#263Method for mapping between virtual CPU and physical CPU and electronic device
#264Memory controller for a network on a chip device
#265DISTRIBUTED MEMORY CONTROLLER
#266MEMORY SYSTEM AND OPERATING METHOD THEREOF
#267MEMORY MODULE HAVING A MEMORY CONTROLLER FOR CONTROLLING NON-VOLATILE MEMORY
#268Flash controller to provide a value that represents a parameter to a flash memory
#269Read training a memory controller
#270Inter-component communication including posted and non-posted transactions
#271Medical device connectivity interface system and method
#272Multiple transaction data flow control unit for high-speed interconnect
#273System and method of interfacing co-processors and input/output devices via a main memory system
#274Memory card and host device thereof
#275Apparatus for monitoring data access to internal memory device and internal memory device
#276I/O channel scrambling/ECC disassociated communication protocol
#277Access controlling method of dual port memory system
#278Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features
#279Method and apparatus for scheduling pipeline of multiprocessor-based motion control software
#280Signal processing device, method of signal processing, storage medium, and electronic musical instrument
#281Multiprocessor cache buffer management
#282Data storage device and method for integrated bridge firmware to be retrieved from a storage system on chip (SOC)
#283Holding by a memory controller multiple central processing unit memory access requests, and performing the multiple central processing unit memory request in one transfer cycle
#284Method and apparatus for performing error handling operations using error signals
#285Method and apparatus for providing a host memory controller write credits for write commands
#286Method and apparatus for using an error signal to indicate a write request error and write request acceptance
#287Optical interconnect in high-speed memory systems
#288ELECTRONIC DEVICE WITH MULTIPLE INTERFACES
#289Semiconductor device including a global buffer shared by a plurality of memory controllers
#290COMPUTER HAVING BUFFERING CIRCUIT FOR HARD DISK DRIVE
#291Method and apparatus for selecting one of a plurality of bus interface configurations to use
#292Managing buffered communication between cores
#293Information processing apparatus, communication method and information processing system for communication of global data shared by information processing apparatuses
#294Method and apparatus for setting high address bits in a memory module
#295Memory Bus Loading and Conditioning Module
#296Memory aggregation device
#297Method and apparatus for a memory module to accept a command in multiple parts
#298Method and apparatus for encoding registers in a memory module
#299Method and apparatus for determining a timing adjustment of output to a host memory controller
#300Memory network to route memory traffic and I/O traffic