190397 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Information transfer, e.g. on bus; Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
Method and device for processing serial binary input by comparing binary digits at even and odd locations of the input
#302File system extension system and method
#303Apparatus and method for adjusting a rate at which data is transferred from a media access controller to a memory in a physical-layer circuit
#304Flash controller to provide a value that represents a parameter to a flash memory
#305Method and apparatus for selecting an interconnect frequency in a computing system
#306Time multiplexing at different rates to access different memory types
#307Memory physical layer interface logic for generating dynamic random access memory (DRAM) commands with programmable delays
#308SEMICONDUCTOR MEMORY CARD, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR MEMORY SYSTEM
#309Modular switched fabric for data storage systems
#310Front end traffic handling in modular switched fabric based data storage systems
#311Failover handling in modular switched fabric for data storage systems
#312Network failover handling in modular switched fabric based data storage systems
#313Removable memory card type detection systems and methods
#314System and Method for Shared Memory for FPGA Based Applications
#315Information processing apparatus and bus control method
#316Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device
#317SYNCHRONIZATION OF ACTIVITY OF MULTIPLE SUBSYSTEMS IN A SoC TO SAVE STATIC POWER
#318Computer architecture having selectable, parallel and serial communication channels between processors and memory
#319Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module
#320System and method of interfacing co-processors and input/output devices via a main memory system
#321Memory mirroring utilizing single write operations
#322Data bus driving circuit, and semiconductor device and semiconductor memory device including the same
#323Memory mirroring
#324Distributed Termination for Flyby Memory Buses
#325Drive message router
#326Traffic-dependent adaptive interrupt moderation
#327MEMORY AND PROCESS SHARING VIA INPUT/OUTPUT WITH VIRTUALIZATION
#328Memory controller, memory system including the same and method of operating memory controller
#329Bus auto-addressing system
#330Data storage raid architecture system and method
#331Network interface device that maps host bus writes of configuration information for virtual NIDs into a small transactional memory
#332Chip storing a value that represents adjustment to output drive strength
#333Chip having port to receive value that represents adjustment to output driver parameter
#334Techniques for inter-component communication based on a state of a chip select pin
#335Chip having port to receive value that represents adjustment to transmission parameter
#336Inter-component communication including posted and non-posted transactions
#337Receive clock calibration for a serial bus
#338Inter-component communication including slave component initiated transaction
#339Inter-component communication including posted and non-posted transactions
#340Transactional memory that performs an ALUT 32-bit lookup operation
#341Semiconductor memory device with plural memory die and controller die
#342Die-stacked memory device with reconfigurable logic
#343Memory device for multiple processors and memory system having the same
#344Memory system
#345System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class
#346Memory controller, computing device with a memory controller, and method for calibrating data transfer of a memory system
#347Inter-component communication using an interface including master and slave communication
#348Read training a memory controller
#349Read training a memory controller
#350Memory extension system and method
#351Method and apparatus for memory command input and control
#352High capacity memory systems with inter-rank skew tolerance
#353Reducing latency of unified memory transactions
#354Method for erasing data entity in memory module
#355Memory system performance configuration
#356Method and system for improving serial port memory communication latency and reliability
#357Memory card and host device thereof
#358Chip having register to store value that represents adjustment to reference voltage
#359Data encoding for non-volatile memory
#360Adaptive latency tolerance for power management of memory bus interfaces
#361Multiple transaction data flow control unit for high-speed interconnect
#362Method for providing a generic interface and microcontroller having a generic interface
#363System and methods for memory expansion
#364Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation
#365Apparatus and method for adjusting bandwidth
#366Data bus inversion apparatus, systems, and methods
#367Adjustment of write timing in a memory device
#368Timing optimized implementation of algorithm to reduce switching rate on high throughput wide buses
#369Transactional memory that performs an ALUT 32-bit lookup operation
#370Configurable embedded memory system
#371Configurable bandwidth memory devices and methods
#372Memory system including nonvolatile memory device and control method thereof
#373Transactional memory that performs an atomic metering command
#374STACKED MEMORY DEVICE WITH HELPER PROCESSOR
#375Chained bus method
#376Bridging device having a configurable virtual page size
#377Method and system for improving serial port memory communication latency and reliability
#378Memory and process sharing across multiple chipsets via input/output with virtualization
#379Memory array with flash and random access memory and method therefor, reading data from the flash memory without storing the data in the random access memory
#380Apparatuses for inter-component communication including slave component initiated transaction
#381System and method for calibration of serial links using a serial-to-parallel loopback
#382Serial advanced technology attachment dual in-line memory module
#383Method and apparatus for memory command input and control
#384Time multiplexing at different rates to access different memory types
#385Chip having register to store value that represents adjustment to reference voltage
#386Configurable bandwidth memory devices and methods
#387Flash memory device comprising host interface for processing a multi-command descriptor block in order to exploit concurrency
#388Semiconductor device
#389Memory system with independently adjustable core and interface data rates
#390System and method of interfacing co-processors and input/output devices via a main memory system
#391Concurrently searching multiple devices of a non-volatile semiconductor memory
#392System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain
#393System and Method for Managing a Memory as a Circular Buffer
#394Portable data carrier having additional functionality
#395System and method for improving throughput of data transfers using a shared non-deterministic bus
#396System and method for facilitating data transfer using a shared non-deterministic bus
#397Using identification in cache memory for parallel requests
#398Method for operating flash memories on a bus
#399DATA TRANSMISSION
#400Bridge device architecture for connecting discrete memory devices to a system
#401Data transmission system, storage medium and data transmission program
#402Apparatus, system, and method for data transformations within a data storage device
#403Detection circuit for mixed asynchronous and synchronous memory operation
#404Data bus inversion apparatus, systems, and methods
#405Adjustable byte lane offset for memory module to reduce skew
#406Flexible selection command for non-volatile memory
#407System and method for memory hub-based expansion bus
#408Balanced on-die termination
#409High-speed interface for daisy-chained devices
#410Memory controller and method utilizing equalization co-efficient setting
#411Mechanism for granting controlled access to a shared resource
#412Semiconductor memory apparatus and data input and output method thereof
#413Configurable bandwidth memory devices and methods
#414Reducing simultaneous switching outputs using data bus inversion signaling
#415Optical interconnect in high-speed memory systems
#416Semiconductor memory device with plural memory die and controller die
#417Flash memory interface
#418SEMICONDUCTOR MEMORY CARD, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR MEMORY SYSTEM
#419System and method for memory hub-based expansion bus
#420Memory card and host device thereof
#421Serially interfaced random access memory
#422RESERVING PCI MEMORY SPACE FOR PCI DEVICES
#423Independent Threading of Memory Devices Disposed on Memory Modules
#424Adjustment of write timing in a memory device
#425Memory Unit Access
#426PARALLEL TRAINING OF DYNAMIC RANDOM ACCESS MEMORY CHANNEL CONTROLLERS
#427Method Allowing Processor with Fewer Pins to Use SDRAM
#428Electronic Devices and Methods for Storing Data in a Memory
#429HIGH BANDWIDTH MEMORY INTERFACE
#430DATA STORAGE SYSTEM COMPRISING MEMORY CONTROLLER AND NONVOLATILE MEMORY
#431METHOD AND APPARATUS FOR CONNECTING MULTIPLE MEMORY DEVICES TO A CONTROLLER
#432Memory device accepting write data and inverted write data from a host circuit
#433Configurable bandwidth memory devices and methods
#434Data protecting method capable of effectively recording protection information and memory using thereof
#435DATA MOVING METHOD AND SYSTEM UTILIZING THE SAME
#436Memory access device including multiple processors
#437Memory apparatuses with low supply voltages
#438Bridging device having a configurable virtual page size
#439Method and system for improving serial port memory communication latency and reliability
#440Self-synchronizing hardware/software interface for multimedia SOC design
#441Bridge device architecture for connecting discrete memory devices to a system
#442Detection circuit for mixed asynchronous and synchronous memory operation
#443Electronic device using memory to expand storage capacity
#444Chained bus method and device
#445System and method for memory hub-based expansion bus
#446Mask key selection based on defined selection criteria
#447NONVOLATILE MEMORY SYSTEM
#448Data bus inversion apparatus, systems, and methods
#449Majority voting logic circuit for dual bus width
#450ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM
#451PROVIDING A VARIABLE FRAME FORMAT PROTOCOL IN A CASCADE INTERCONNECTED MEMORY SYSTEM
#452PSEUDO-RANDOM BIT SEQUENCE (PRBS) SYNCHRONIZATION FOR INTERCONNECTS WITH DUAL-TAP SCRAMBLING DEVICES
#453System and dynamic random access memory device having a receiver
#454Registered DIMM memory system
#455MICROPROCESSOR COUPLED TO MULTI-PORT MEMORY
#456CASCADED MEMORY ARRANGEMENT
#457Data bus inversion apparatus, systems, and methods
#458System and methods for memory expansion
#459Memory card and host device thereof
#460Memory card and host device thereof
#461Data access system and data access method
#462Deriving clocks in a memory system
#463Implementing Asynchronous Request for Forcing Dynamic Memory into Self Refresh
#464MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORY
#465System for transferring information and method thereof
#466Adjustable byte lane offset for memory module to reduce skew
#467SEMICONDUCTOR MEMORY CARD, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR MEMORY SYSTEM
#468Fully buffered DIMM read data substitution for write acknowledgement
#469IC with MMW transceiver communications
#470Device directed memory barriers
#471Semiconductor memory system having volatile memory and non-volatile memory that share bus, and method of controlling operation of non-volatile memory
#472Mechanism for granting controlled access to a shared resource
#473APPLICATION PROCESSORS AND MEMORY ARCHITECTURE FOR WIRELESS APPLICATIONS
#474System and method for memory hub-based expansion bus
#475HIGH-SPEED OPTICAL CONNECTION BETWEEN CENTRAL PROCESSING UNIT AND REMOTELY LOCATED RANDOM ACCESS MEMORY
#476Semiconductor memory module and memory system, and method of communicating therein
#477Data sampling clock edge placement training for high speed GPU-memory interface
#478MEMORY SYSTEM AND METHOD ACCESSING MEMORY ARRAY VIA COMMON SIGNAL PORTS
#479Staggered interleaved memory access
#480Alignment-unit-based virtual formatting methods and devices employing the methods
#481Flexible selection command for non-volatile memory
#482High bandwidth memory interface
#483Apparatuses for synchronous transfer of information
#484MEMORY SYSTEM HAVING BASEBOARD LOCATED MEMORY BUFFER UNIT
#485Integrated circuit device and signaling method with phase control based on information in external memory device
#486Method and apparatus for sending data from a memory
#487High bandwidth memory interface
#488Integrated circuit memory device and signaling method for adjusting drive strength based on topography of integrated circuit devices
#489Integrated circuit device and signaling method with topographic dependent equalization coefficient
#490Data processing system
#491Method and System for Facilitating Faster Data Transmission between a Central Processing Unit and a Connected Memory Device
#492Data Communications with an Integrated Circuit
#493Control device and control method for memory
#494Method and apparatus for scrubbing memory
#495Computer system to control the data transfer between a memory and a peripheral device connected to a CPU via a bus
#496Adaptive speed control for MAC-PHY interfaces
#497Integrated Circuit Device that Stores a Value Representative of an Equalization Co-Efficient Setting
#498Detection circuit for mixed asynchronous and synchronous memory operation
#499System and method for memory hub-based expansion bus
#500Semiconductor storage device and storage system
#501Nonvolatile memory system
#502Fully buffered DIMM read data substitution for write acknowledgement
#503Self-synchronizing hardware/software interface for multimedia SOC design
#504High speed data bus
#505System, method and storage medium for deriving clocks in a memory system
#506Write data mask method and system
#507Method and apparatus for dynamic optimization of connection establishment and message progress processing in a multifabric MPI implementation
#508Serially interfaced random access memory
#509Memory card and host device thereof
#510Memory single-to-multi load repeater architecture
#511COMPUTING SYSTEM AND METHOD OF ENABLING A DIGITAL SIGNAL PROCESSOR TO ACCESS PARAMETER TABLES THROUGH A CENTRAL PROCESSING UNIT
#512Adjustable byte lane offset for memory module to reduce skew
#513Generating and verifying read and write cycles in a PCI bus system
#514System and method for memory hub-based expansion bus
#515High speed data bus
#516Multi-memory chip and data transfer method capable of directly transferring data between internal memory devices
#517Die-to-die interconnect interface and protocol for stacked semiconductor dies
#518System and method for memory hub-based expansion bus
#519System and method for memory hub-based expansion bus
#520Detection circuit for mixed asynchronous and synchronous memory operation
#521Method and apparatus for self-adjusting input delay in DDR-based memory systems
#522System and method for improved memory performance in a mobile device
#523Measure controlled delay with duty cycle control
#524Method to mitigate performance turnaround in a bidirectional interconnect
#525Side-by-side inverted memory address and command buses
#526Apparatus and method for generating a variable-frequency clock
#527High speed data bus
#528Data sampling clock edge placement training for high speed GPU-memory interface
#529Integrated circuit device that stores a value representative of an equalization co-efficient setting
#530Method and System For A Variable Frequency SDRAM Controller
#531Method for ensuring optimal memory configuration in a computer
#532High speed data bus
#533System and method for memory hub-based expansion bus
#534Non-volatile memory device architecture, for instance a flash kind, having a serial communication interface
#535Detection circuit for mixed asynchronous and synchronous memory operation
#536Method for transmitting data via a data bus
#537Apparatus and method for topography dependent signaling
#538Semiconductor memory device and memory system
#539Method and apparatus for maintaining data density for derived clocking
#540Backward-compatible parallel DDR bus for use in host-daughtercard interface
#541High bandwidth memory interface
#542Method and apparatus for transmitting and storing data
#543High speed data bus
#544Flexible memory interface system for independently processing different portions of an instruction
#545Multi-port SRAM system for a distributed memory pool
#546Multi-bus replicator using RF serializer/deserializer for chip-to-chip interconnect
#547Byte-addressable device and computing system including same
#548Memory validation
#549Storage adapter device for communicating with network storage
#550Memory validation
#551Efficient management of bus bandwidth for multiple drivers
#552I3C read from long latency devices
#553PCIe fabric enabled peer-to-peer communications
#554Storage adapter device for communicating with network storage
#555Systems and methods for memory FIFO control
#556Wide programmable gain receiver data path for single-ended memory interface application
#557Method and apparatus for background memory subsystem calibration
#558Memory modules with nonvolatile storage and rapid, sustained transfer rates
#559Controlling exclusive access using supplemental transaction identifiers
#560Dynamically adjusting read data return sizes based on memory interface bus utilization
#561Dynamic ingestion throttling of data log
#562Method and apparatus for memory access
#563Multipath I/O in a computer system
#564Scalable 2.5D interface circuitry
#565Event-based in-band host registration
#566Storage adapter device for communicating with network storage
#567Transactional memory that performs an atomic metering command
#568Hybrid architecture for signal processing and signal processing accelerator
#569Flash/DRAM/embedded DRAM-equipped system and method
#570Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system
#571Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory
#572Update packet sequence number packet ready command
#573Enhanced computer processor and memory management architecture