191218 ⎘
Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled; Indexing scheme relating to groups -; Details concerning the type of numbers or the way they are handled; Devices capable of handling different types of numbers Reconfigurable for different fixed word lengths
Reconfigurable Processor Circuit Architecture
#2DYNAMIC PRECISION MANAGEMENT FOR INTEGER DEEP LEARNING PRIMITIVES
#3OPTIMIZED COMPUTE HARDWARE FOR MACHINE LEARNING OPERATIONS
#4INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS
#5RECONFIGURABLE ARITHMETIC ENGINE CIRCUIT
#6ARITHMETIC APPARATUS, OPERATING METHOD THEREOF, AND NEURAL NETWORK PROCESSOR
#7DYNAMIC PRECISION MANAGEMENT FOR INTEGER DEEP LEARNING PRIMITIVES
#8Reconfigurable Processor Circuit Architecture
#9Reconfigurable arithmetic engine circuit
#10Instructions for fused multiply-add operations with variable precision input operands
#11Dynamic precision management for integer deep learning primitives
#12INTEGRATED CIRCUITS WITH MACHINE LEARNING EXTENSIONS
#13Reconfigurable processor circuit architecture
#14Reconfigurable processor circuit architecture
#15Optimized compute hardware for machine learning operations
#16Dynamic precision management for integer deep learning primitives
#17Instructions for fused multiply-add operations with variable precision input operands
#18Integrated circuits with machine learning extensions
#19Integrated circuits with machine learning extensions
#20Multiplication and accumulation (MAC) operator
#21Neural network system with multiplication and accumulation(MAC) operator
#22Arithmetic apparatus, operating method thereof, and neural network processor
#23Dynamic precision management for integer deep learning primitives
#24Reconfigurable processor circuit architecture
#25Reconfigurable arithmetic engine circuit
#26Variable accuracy computing system
#27Dynamic precision management for integer deep learning primitives
#28Instructions for fused multiply-add operations with variable precision input operands
#29Variable precision floating-point multiplier
#30Variable precision floating-point multiplier
#31Apparatuses for integrating arithmetic with logic operations
#32Dynamic, variable bit-width numerical precision on field-programmable gate arrays for machine learning tasks
#33Integrated circuits with machine learning extensions
#34Integrated circuits with machine learning extensions
#35FP16-S7E8 mixed precision for deep learning and other algorithms
#36Reconfigurable multi-precision integer dot-product hardware accelerator for machine-learning applications
#37Systems, methods, and apparatuses utilizing an elastic floating-point number
#38Instructions for fused multiply-add operations with variable precision input operands
#39Reduced floating-point precision arithmetic circuitry
#40Apparatuses for integrating arithmetic with logic operations
#41Dynamic precision management for integer deep learning primitives
#42Variable precision floating-point multiplier
#43Processing circuit capable of dynamically modifying its precision
#44Methods for calculating floating-point operands and apparatuses using the same
#45Comparator and memory region detection circuitry and methods
#46Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof
#47Variable precision floating-point multiplier
#48FLOATING POINT MULTIPLY ACCUMULATOR MULTI-PRECISION MANTISSA ALIGNER
#49Precision data access using differential data
#50Splitable and scalable normalizer for vector data
#51Precision data access using differential data
#52Floating point multiply accumulator multi-precision mantissa aligner
#53Number format pre-conversion instructions
#54Performing arithmetic operations using both large and small floating point values
#55Vector processing engines having programmable data path configurations for providing multi-mode radix-2butterfly vector processing circuits, and related vector processors, systems, and methods
#56Adder capable of supporting addition and subtraction of up to n-bit data and method of supporting addition and subtraction of a plurality of data type using the adder
#57Variable precision floating point multiply-add circuit
#58Method and apparatus for multiplying binary operands
#59Method and apparatus for multiply instructions in data processors
#60Dynamic range adjusting floating point execution unit
#61Performing arithmetic operations using both large and small floating point values
#62Performing arithmetic operations using both large and small floating point values
#63Floating point multiply accumulator multi-precision mantissa aligner
#64Multi-mode combined rotator
#65Double precision approximation of a single precision operation
#66System and method to implement a matrix multiply unit of a broadband processor
#67Number format pre-conversion instructions
#68Reducing power consumption in multi-precision floating point multipliers
#69Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product
#70Dual Mode Floating Point Multiply Accumulate Unit
#71Multi-phased computational reconfiguration
#72Extended-precision integer arithmetic and logical instructions
#73Method and system for multi-precision computation
#74Processor and method for implementing instruction support for multiplication of large operands
#75Digital signal processing circuitry with redundancy and bidirectional data paths
#76Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
#77ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF
#78LARGE INTEGER SUPPORT IN VECTOR OPERATIONS
#79Dynamic range adjusting floating point execution unit
#80Packed add-subtract operation in a microprocessor
#81Method and apparatus for multiplying binary operands
#82Circuit and method for performing multiple modulo mathematic operations
#83System and method to implement a matrix multiply unit of a broadband processor
#84Unified integer/galois field (2m) multiplier architecture for elliptic-curve crytpography
#85Universal execution unit
#86MULTIPLY AND MULTIPLY AND ACCUMULATE UNIT
#87Multi-format multiplier unit
#88Floating Point Addition
#89Selectively isolating processor elements into subsets of processor elements
#90Long Instruction Word Controlling Plural Independent Processor Operations
#91Device and method for calculating a result of a modular multiplication with a calculating unit smaller than the operands
#92Systems and Methods for Implementing a Double Precision Arithmetic Memory Architecture
#93Controlled-precision iterative arithmetic logic unit
#94Multiplier and arithmetic unit
#95Packed add-subtract operation in a microprocessor
#96Stream Processor with Variable Single Instruction Multiple Data (SIMD) Factor and Common Special Function
#97Dual mode floating point multiply accumulate unit
#98Arithmetic operation unit, information processing apparatus and arithmetic operation method
#99Interconnect switch assembly with input and output ports switch coupling to processor or memory pair and to neighbor ports coupling to adjacent pairs switch assemblies
#100Floating-point processor for processing single-precision numbers
#101Method and apparatus of dsp resource allocation and use
#102Method and system for performing digital signal processing operations in a computer system
#103Low power array multiplier
#104System and method for a floating point unit with feedback prior to normalization and rounding
#105Data processing circuit, multiplier unit with pipeline, ALU and shift register unit for use in a data processing circuit
#106Modular multipliers having segmentable structure and cryptography systems utilizing same
#107Circuit and method for performing multiple modulo mathematic operations
#108Circuit and method for performing multiple modulo mathematic operations
#109Reconfigurable circuit with programmable split adder
#110Method and system for performing parallel integer multiply accumulate operations on packed data
#111Arithmetic processor for accomodating different field sizes
#112Method for performing single instruction multiple data operations on packed data
#113System and method for DMA transfer of data in scatter/gather mode
#114Method and system for performing parallel integer multiply accumulate operations on packed data
#115Double-precision floating-point operation
#116Low power optimizations for a floating point multiplier