MULTIPLY-ACCUMULATE WITH VARIABLE FLOATING POINT PRECISION

Process for dual mode floating point multiplier-accumulator with high precision mode for near zero accumulation results

Process for performing floating point multiply-accumulate operations with precision based on exponent differences for saving power

Power saving floating point multiplier-accumulator with precision-aware accumulation

MAC Processing Pipelines, Circuitry to Configure Same, and Methods of Operating Same

Configurable MAC pipelines for finite-impulse-response filtering, and methods of operating same

Multiplier-Accumulator Circuitry and Pipeline using Floating Point Data, and Methods of using Same

Floating-point number operation circuit and method

Implementing logarithmic and antilogarithmic operations based on piecewise linear approximation

Arithmetic apparatus and control method of the same using cordic algorithm

Math processing by detection of elementary valued operands

Method for the on-line testing of pipeline stages temporarily not in use, and associated device

Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values

Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values

Dual-path fused floating-point add-subtract

Method and apparatus for multiply instructions in data processors

Pipelined vectoring-mode CORDIC

Pipelined divide circuit for small operand sizes

System and method of bypassing unrounded results in a multiply-add pipeline unit

Processor pipeline which implements fused and unfused multiply-add instructions

Reducing power consumption in multi-precision floating point multipliers

Performing multiplication for a multi-channel notch rejection filter

Multi-phased computational reconfiguration

Mode-based multiply-add recoding for denormal operands

Hardware Function Generator Support in a DSP

Serially connected processing elements having forward and reverse processing time intervals

Flexible accumulator in digital signal processing circuitry

Processor which implements fused and unfused multiply-add instructions in a pipelined manner

MODULAR REDUCTION OPERATOR

Method for implementing montgomery modular multiplication and device therefore

Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system

Calculating apparatus having a plurality of stages

Multi-stage floating-point accumulator

Mode-based multiply-add recoding for denormal operands

High-performance RISC-DSP

Scalable, faster method and apparatus for montgomery multiplication

Reduction calculations in elliptic curve cryptography

Reciprocal estimate computation methods and apparatus

Mixed mode floating-point pipeline with extended functions

Fused multiply add split for multiple precision arithmetic

Copying of unaligned data in a pipelined operation

Simple and amended saturation for pipelined arithmetic processors

Hardware function generator support in a DSP

Method and system for pipelining saturated accumulation and other loops with loop-carried dependencies

Hybrid arithmetic logic unit

Data processing apparatus and method for performing floating point addition

Data processing apparatus

Methods and apparatus for pipeline processing of encryption data

Data processing circuit, multiplier unit with pipeline, ALU and shift register unit for use in a data processing circuit

Logical calculation circuit, logical calculation device, and logical calculation method

Circuit for recursively calculating data

Method and apparatus for performing Montgomery multiplications

Information processing device, method, and program

Flexible accumulator in digital signal processing circuitry

Pipelined accumulators