191457 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures Employing a main memory using a specific memory technology
Sub-classes:METHOD FOR MEMORY ALLOCATION DURING EXECUTION OF A NEURAL NETWORK
#2CODECS FOR DNA DATA STORAGE
#3Storage System and Method for Accessing Same
#4Storage system and method for accessing same
#5METHOD FOR MEMORY ALLOCATION DURING EXECUTION OF A NEURAL NETWORK
#6Storage system and method for accessing same
#7METHOD AND APPARATUS FOR MEMORY MANAGEMENT
#8METHOD AND APPARATUS FOR MEMORY MANAGEMENT
#9PREFETCH MODULE FOR HIGH THROUGHPUT MEMORY TRANSFERS
#10MAPPING TABLE MANAGEMENT METHOD FOR SOLID STATE STORAGE DEVICE
#11DRAM and method of operating the same in an hierarchical memory system
#12METHOD AND APPARATUS FOR MEMORY MANAGEMENT
#13Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory
#14METHOD AND APPARATUS FOR MEMORY MANAGEMENT
#15Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems
#16METHOD AND APPARATUS FOR MEMORY MANAGEMENT
#17Method and device for protecting dynamic random access memory
#18Method of controlling memory cell access based on safe address mapping
#19INSTRUCTION AND LOGIC TO PREFETCH INFORMATION FROM A PERSISTENT MEMORY
#20SYSTEM AND METHOD FOR PAGE-BY-PAGE MEMORY CHANNEL INTERLEAVING
#21Method for refreshing dynamic random access memory and a computer system
#22Efficient configuration of memory components
#23INFORMATION RECORDING DEVICE AND DATA ERASING METHOD
#24MEMORY INTERLEAVING ON MEMORY CHANNELS
#25Instruction and logic to test transactional execution status
#26Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory
#27Instruction and logic to test transactional execution status
#28Instruction and logic to test transactional execution status
#29Instruction and logic to test transactional execution status
#30Instruction and logic to test transactional execution status
#31System and method for achieving atomicity in ternary content-addressable memories
#32Instruction and logic to test transactional execution status
#33Storage controlling system and storage controlling apparatus
#34Electronic device and method for controlling shareable cache memory thereof
#35System and method for managing pipelines in reconfigurable integrated circuit architectures
#36Priority queue having array and trees
#37Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory
#38Data buffer with strobe-based primary interface and a strobe-less secondary interface
#39Kernel key handling
#40Final level cache system and corresponding methods
#41Apparatus, system and method for managing space in a storage device
#42Method and apparatus for memory management
#43Managing system-wide encryption keys for data storage systems