191463 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Employing a main memory using a specific memory technology Memory mapped I/O
POWER REDUCTION IN AN ARRAY OF DATA PROCESSING ENGINES
#2MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS
#3SYSTEMS AND METHODS FOR POLICY EXECUTION PROCESSING
#4Method and system for solid state drive (SSD)-based redundant array of independent disks (RAID)
#5Systems and methods for policy execution processing
#6FAST MEMORY MAPPED IO SUPPORT BY REGISTER SWITCH
#7Method, system, and apparatus for supporting multiple address spaces to facilitate data movement
#8DATA TRANSMISSION METHOD AND APPARATUS
#9Method and NMP DIMM for managing address map
#10Memory devices and methods which may facilitate tensor memory access
#11System and method for improved performance in a multidimensional database environment
#12Direct access to host memory for guests
#13Method, system, and apparatus for supporting multiple address spaces to facilitate data movement
#14Resource allocation in a multi-processor system
#15Systems and methods for policy execution processing
#16System on chip, access command routing method, and terminal
#17Mechanism to dynamically allocate physical storage device resources in virtualized environments
#18Mechanism to dynamically allocate physical storage device resources in virtualized environments
#19Memory devices and methods which may facilitate tensor memory access
#20Method, device, and computer program product for managing address mapping in storage system
#21Direct access to host memory for guests
#22Resource allocation in a multi-processor system
#23METHOD AND SYSTEM FOR INPUT/OUTPUT PROCESSING FOR WRITE THROUGH TO ENABLE HARDWARE ACCELERATION
#24Cost-effective deployments of a PMEM-based DMO system
#25Memory devices and methods which may facilitate tensor memory access
#26Integrating host-side storage device management with host-side non-volatile memory
#27System and method for improved performance in a multidimensional database environment
#28Methods and apparatus for host register access for data storage controllers for ongoing standards compliance
#29Systems and methods for policy execution processing
#30Computing device having two trusted platform modules
#31MANAGEMENT CONTROLLER-BASED SOLUTION FOR PROCESSOR RAS IN SMI-FREE ENVIRONMENT
#32Hypervisor direct memory access
#33Nested hypervisor memory virtualization
#34Methods and apparatus to utilize non-volatile memory for computer system boot
#35Efficient enforcement of barriers with respect to memory move sequences
#36File system for shingled magnetic recording (SMR)
#37Forced detaching of applications from DMA-capable PCI mapped devices
#38Permuted memory access mapping
#39Mechanism to dynamically allocate physical storage device resources in virtualized environments
#40Computing device, data transfer method between coprocessor and non-volatile memory, and computer-readable recording medium
#41Managing guest partition access to physical devices
#42Secure zero-copy packet forwarding
#43Two level addressing in storage clusters
#44Method, device, and system for implementing hardware acceleration processing
#45Memory move instruction sequence targeting an accelerator switchboard
#46Memory move instruction sequence including a stream of copy-type and paste-type instructions
#47Low latency efficient sharing of resources in multi-server ecosystems
#48Circuit and method of power on initialization for configuration memory of FPGA
#49System and method for improved performance in a multidimensional database environment
#50Low latency efficient sharing of resources in multi-server ecosystems
#51System on-chip and electronic device including the same
#52System and method for achieving high performance data flow among user space processes in storage systems
#53Controllers including separate input-output circuits for mapping table and buffer memory, solid state drives including the controllers, and computing systems including the solid state drives
#54Memory mapping in a processor having multiple programmable units
#55Memory mapping in a processor having multiple programmable units
#56Systems and methods for expanding memory for a system on chip
#57Memory mapping in a processor having multiple programmable units
#58Two level addressing in storage clusters
#59Memory mapping in a processor having multiple programmable units
#60System and method for executing native client code in a storage device
#61Transactional memory
#62Enabling virtualization of a processor resource
#63Two level addressing in storage clusters
#64Memory access scheme for system on chip
#65SYSTEMS AND METHODS FOR DURABLE DATABASE OPERATIONS IN A MEMORY-MAPPED ENVIRONMENT
#66Data encoding for non-volatile memory
#67Memory mapping in a processor having multiple programmable units
#68Block-based storage device with a memory-mapped interface
#69Information processing apparatus and access control method
#70Hybrid exclusive multi-level memory architecture with memory management
#71Data encoding for non-volatile memory
#72Data encoding for non-volatile memory
#73Data encoding for non-volatile memory
#74Data encoding for non-volatile memory
#75Enabling virtualization of a processor resource
#76Implementing user mode foreign device attachment to memory channel
#77Translation of input/output addresses to memory addresses
#78Enabling virtualization of a processor resource
#79Two level addressing in storage clusters
#80Accessing a logic device through a serial interface
#81METHODS AND APPARATUS FOR INCREASING DEVICE ACCESS PERFORMANCE IN DATA PROCESSING SYSTEMS
#82Systems and methods for durable database operations in a memory-mapped environment
#83Translation of input/output addresses to memory addresses
#84Control of on-die system fabric blocks
#85Transactional memory
#86Translation of input/output addresses to memory addresses
#87Hierarchical to physical memory mapped input/output translation
#88Control of on-die system fabric blocks
#89System and method of host request mapping
#90Input-output virtualization technique
#91Method and apparatus of implementing control and status registers using coherent system memory
#92System and method for achieving high performance data flow among user space processes in storage system
#93Accessing control and status register (CSR)
#94Placing virtual machine monitor (VMM) code in guest context to speed memory mapped input/output virtualization
#95Multipath accessible semiconductor memory device having shared register and method of operating thereof
#96Configurable memory system and method for providing atomic counting operations in a memory device
#97Method for accessing memory
#98Filtering and remapping interrupts
#99Efficiently controlling special memory mapped system accesses
#100Method for Accessing Control Registers via a Memory Device
#101Information processing apparatus and memory address space allocation method
#102Address space emulation
#103Allocation of differently sized memory address ranges to input/output endpoints in memory mapped input/output fabric based upon determined locations of input/output endpoints
#104Simulation of a PCI device's memory-mapped I/O registers
#105Method, system, and program for transferring data directed to virtual memory addresses to a device memory
#106Memory mapped input/output virtualization
#107Accommodating multiple operating systems and memory sizes on IA-32 platforms
#108Location-based non-uniform allocation of memory resources in memory mapped input/output fabric