191481 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Using a specific main memory architecture Centralized memory
Sub-classes:MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS
#2NETWORK DEVICE FOR USE IN A COMMUNICATION NETWORK AND METHOD OF MANUFACTURING A NETWORK DEVICE
#3Memory devices and methods which may facilitate tensor memory access
#4Memory devices and methods which may facilitate tensor memory access
#5Memory devices and methods which may facilitate tensor memory access
#6Profiling cache replacement
#7System and method for automated data organization in a storage system
#8METHOD AND ELECTRONIC DEVICE FOR ALLOCATING DYNAMIC MEMORY RESOURCES
#9Method and apparatus for defect management in a non-volatile memory device
#10System on-chip and electronic device including the same
#11Control device for a motor vehicle
#12System and method of conducting in-place write operations in a shingled magnetic recording (SMR) drive
#13Hybrid-HDD that limits dirty data in NAND
#14DISK APPARATUS AND CONTROL METHOD
#15Memory system and SoC including linear remapper and access window
#16Electronic device and a method for managing memory space thereof
#17Unmap storage space
#18Write reordering in a hybrid disk drive
#19Heterogeneous unified memory
#20Memory updating in a dual-ported internal memory with concurrent transfer and retrieval
#21Method of collecting garbage blocks in a solid state drive
#22Linear recording executing optimum writing upon receipt of series of commands including mixed read and write commands
#23Adjusting allocation of storage devices
#24FLASH MEMORY BASED STORAGE SYSTEM AND OPERATING METHOD
#25Optimizing configuration memory by sequentially mapping the generated configuration data into fields having different sizes by determining regular encoding is not possible
#26Virtual memory structure for coprocessors having memory allocation limitations
#27WRITE REORDERING IN A HYBRID DISK DRIVE
#28Demand paging method for mobile terminal, controller and mobile terminal
#29Managing addressable memory in heterogeneous multicore processors
#30Hybrid caching techniques and garbage collection using hybrid caching techniques
#31INFORMATION PROCESSING DEVICE
#32High speed memory access in an embedded system
#33System with internal memory for storing data or a portion of data written to external memory
#34Hierarchical memory addressing
#35Computing system and method controlling memory of computing system
#36Method and system for loading application to a local memory of a co-processor system by using position independent loader
#37Processor task and data management
#38Cached memory system and cache controller for embedded digital signal processor
#39Device having data sharing capabilities and a method for sharing data
#40Hybrid caching techniques and garbage collection using hybrid caching techniques
#41Processor and method for controlling memory
#42High speed memory access in an embedded system
#43Processor task and data management
#44Fast image loading mechanism in cell SPU
#45Operating a dual-ported internal memory
#46Local Memory And Main Memory Management In A Data Processing System
#47Dynamic loading and unloading for processing unit
#48Controlling virtual memory in a storage controller
#49Methods and arrangements to manage on-chip memory to reduce memory latency
#50Apparatus and method for efficient caching via addition of branch into program block being processed
#51Apparatus and method for information processing enabling fast access to program
#52Multi-component processor
#53Memory compression method and apparatus for heterogeneous processor architectures in an information handling system
#54Virtual on-chip memory
#55Cell processor task and data management
#56Task manager with stored task definition having pointer to a memory address containing required code data related to the task for execution
#57Methods and apparatus for facilitating coherency management in distributed multi-processor system
#58Methods and arrangements to manage on-chip memory to reduce memory latency
#59Dynamic loading and unloading for processing unit
#60Cached memory system and cache controller for embedded digital signal processor
#61Shared-memory multiprocessor
#62METHOD FOR CONTROLLING AN INSTRUCTION MEMORY OF AN EMBEDDED SYSTEM
#63Cacheable DMA
#64Dynamic FPGA re-configuration using a virtual FPGA controller
#65Read command processing for data storage system based on previous writes