LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

DYNAMIC I/O VIRTUALIZATION SYSTEM HAVING GUEST MEMORY MANAGEMENT FOR MAPPING VIRTUAL ADDRESSES USING VIRTUALIZATION APPLICATION PROGRAMMING INTERFACE (API) IN GUEST KERNAL

Dynamic I/O virtualization system having guest memory management for mapping virtual addresses using virtualization application programming interface (API) in guest kernal

LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

Dynamic I/O virtualization system having guest memory management for mapping virtual addresses using virtualization application programming interface (API) in guest kernal

Security of dynamic I/O virtualization system having a bidirectional extended hybrid address space (EHAS) for allowing host kernel to access guest memory

Lookahead priority collection to support priority elevation

Read cache memory

Information processor with tightly coupled smart memory unit

Dynamic I/O virtualization system having guest memory management for mapping virtual addresses in a hybrid address space

Sequential memory access operations

Dynamic I/O virtualization system having guest memory management agent (MMA) for resolving page faults using hypercall to map a machine page into host memory

Lookahead priority collection to support priority elevation

Permuted memory access mapping

Dynamic I/O virtualization system having a bidirectional extended hybrid address space (EHAS) for allowing host kernel to access guest memory

Sequential memory access operations

Method and system for valid memory module configuration and verification

Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device

Method for optimising memory writing in a device

Data movement between volatile and non-volatile memory in a read cache memory

Routing direct memory access requests in a virtualized computing environment

Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device

Sequential memory access operations

Information processor with tightly coupled smart memory unit

Non-binary rank multiplication of memory module

Using memory compression to reduce memory commit charge

Method and apparatus for performing error handling operations using error signals

Method and apparatus for providing a host memory controller write credits for write commands

Method and apparatus for using an error signal to indicate a write request error and write request acceptance

Method and apparatus for selecting one of a plurality of bus interface configurations to use

Peripheral register parameter refreshing

Method and apparatus for setting high address bits in a memory module

Caching methods and systems using a network interface card

Methods and systems for accessing storage using a network interface card

Method and apparatus for a memory module to accept a command in multiple parts

Method and apparatus for encoding registers in a memory module

Information handling system secret protection across multiple memory devices

Method and apparatus for determining a timing adjustment of output to a host memory controller

Optimizing replication by distinguishing user and system write activity

Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein

Host and computer system having the same

Memory transfer of objects in a data storage device

Memory access method, buffer scheduler and memory module

Sequential memory access operations

OFFSET RANGE OPERATION STRIPING TO IMPROVE CONCURRENCY OF EXECUTION AND REDUCE CONTENTION AMONG RESOURCES

Information processor with tightly coupled smart memory unit

Data transfer control apparatus

Semiconductor device, semiconductor system and system on chip

Data input/output (I/O) handling for computer network communications links

ROUTING DIRECT MEMORY ACCESS REQUESTS IN A VIRTUALIZED COMPUTING ENVIRONMENT

Memory data transfer method and system

Buffered automated flash controller connected directly to processor memory bus

Programmable address-based write-through cache control

Mid-thread pre-emption with software assisted context switch

Efficient search key controller with standard bus interface, external memory interface, and interlaken lookaside interface

COMPUTING SYSTEM AND OPERATING METHOD OF THE SAME

STORAGE DEVICE AND ADDRESS-CORRESPONDING METHOD, DATA-ACCESSING METHOD, AND IDENTIFYING AND ACCESSING METHOD THEREOF

Sidecar SRAM for high granularity in floor plan aspect ratio

Controller for controlling non-volatile memory and semiconductor device including the same

Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system

SYSTEM AND METHOD FOR HOST-PROCESSOR COMMUNICATION OVER A BUS

Read cache memory with DRAM class promotion

Memory control unit and data storage device including the same

MEMORY AND PROCESS SHARING VIA INPUT/OUTPUT WITH VIRTUALIZATION

Data transfer control device and memory-containing device

Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

Dynamic single root I/O virtualization (SR-IOV) processes system calls request to devices attached to host

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Memory system

Method of processing data with an array of data processors according to application ID

Information processing apparatus, control method for the same, program for the same, and storage medium

Memory architecture determining the number of replicas stored in memory banks or devices according to a packet size

Multi-processor bus and cache interconnection system

Reducing effective cycle time in accessing memory modules

Memory system and an apparatus

System and method to reduce memory access latencies using selective replication across multiple memory ports

Memory and process sharing across multiple chipsets via input/output with virtualization

Power reduction in server memory system

MEMORY MODULE, BOARD ASSEMBLY AND MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE MEMORY SYSTEM

System and method to reduce memory access latencies using selective replication across multiple memory ports

Integer and half clock step division digital variable clock divider

Managing bandwidth allocation in a processing node using distributed arbitration

Lookahead Priority Collection to Support Priority Elevation

Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performance

Method and device for writing block data to an embedded DRAM free of address conflicts

Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines

Priority based exception mechanism for multi-level cache controller

Programmable mapping of external requestors to privilege classes for access protection

Cache pre-allocation of ways for pipelined allocate requests

Memory attribute sharing between differing cache levels of multilevel cache

Mechanism to Update the Status of In-Flight Cache Coherence In a Multi-Level Cache Hierarchy

Programmable address-based write-through cache control

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Hazard prevention for data conflicts between level one data cache line allocates and snoop writes

Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system

Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU

Floating point multiplier circuit with optimized rounding calculation

Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme

Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers

Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stalls

Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty

Distributed user controlled multilevel block and global cache coherence with accurate completion status

Memory data transfer method and system

Processor with tightly coupled smart memory unit

Dual register data path architecture with registers in a data file divided into groups and sub-groups

Cache with multiple access pipelines

Transaction info bypass for nodes coupled to an interconnect fabric

Interleaved Memory Access from Multiple Requesters

Requester based transaction status reporting in a system with multi-level memory

Closed loop adaptive voltage scaling

Memory data transfer method and system

Systems and methods for translating memory addresses

Non-power of two memory configuration

Multibank queuing system

Utilizing a cache mechanism by copying a data set from a cache-disabled memory location to a cache-enabled memory location

Power saving mechanisms for a dynamic mirror service policy

Systems and methods for automatically aggregating write requests

Non-volatile memory device application programming interface

Multi-bank non-volatile memory apparatus with high-speed bus

Systems and methods for automatic generation of parallel data processing code

Systems and methods to distributively process a plurality of data sets stored on a plurality of memory modules