191651 ⎘
Methods for layout verification for polysilicon cell edge structures in FinFET standard cells using filters
#302Assembly workability evaluation calculation device and assembly workability evaluation method
#303Routing standard cell-based integrated circuits
#304IR-aware sneak routing
#305Methods for static checking of asynchronous clock domain crossings
#306Method and system for overlay control
#307Transformer synthesis and optimization in integrated circuit design
#308Determining a user-specified location in a graphical user interface of an electronic design automation tool
#309Calculating circuit-level leakage using three dimensional technology computer aided design and a reduced number of transistors
#310Designing a physical system constrained by equations
#311Identifying layout pattern candidates
#312Detailed placement with search and repair
#313Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout
#314Boundary latch and logic placement to satisfy timing constraints
#315System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks
#316Reduced backdrilling with quarter wavelength transmission line stubs
#317Automatic motion of a computer-aided design model
#318Top-down CAD design
#319EMI SUPPRESSION TECHNIQUE USING A TRANSMISSION LINE GRATING
#320WEAK POINTS AUTO-CORRECTION PROCESS FOR OPC TAPE-OUT
#321Verification of asynchronous clock domain crossings
#322Circuit design evaluation with compact multi-waveform representations
#323Static checking of asynchronous clock domain crossings
#324Conditional phase algebra for clock analysis
#325Clock-gating phase algebra for clock analysis
#326Glitch-aware phase algebra for clock analysis
#327Horizontal optimization of transport alignments
#328Layout design for electron-beam high volume manufacturing
#329Semiconductor device design methods and conductive bump pattern enhancement methods
#330Method and system for repairing wafer defects
#331Robotics connector
#332Structure for logic circuit and serializer-deserializer stack
#333System for designing network on chip interconnect arrangements
#334Register clustering for clock network topology generation
#335Chip level critical point analysis with manufacturer specific data
#336LIGHT EMITTING DEVICE, ELECTRONIC APPARATUS, AND DESIGN METHOD OF SEMICONDUCTOR DEVICE
#337Method of converting between non-volatile memory technologies and system for implementing the method
#338Method of freeform imaging lens
#339Separation and minimum wire length constrained maze routing method and system
#340Hierarchical Approach to Triple Patterning Decomposition
#341Optimization of source, mask and projection optics
#342Method of repeater chip
#343Integrated circuit layout design methodology with process variation bands
#344Method and system for overlay control
#345Power rail layout for dense standard cell library
#346Detecting and displaying multi-patterning fix guidance
#347Capacitor arrangement assisting method and capacitor arrangement assisting device
#348Method for displaying timing information of an integrated circuit floorplan in real time
#349Retargeting semiconductor device shapes for multiple patterning processes
#350Solving an optimization problem using a constraints solver
#351Method and system for reproducing prototyping failures in emulation
#352System and method for series and parallel combinations of electrical elements
#353Updating pin locations in a graphical user interface of an electronic design automation tool
#354Determining a set of timing paths for creating a circuit abstraction
#355Graphical specification and constraint language for developing programs for hardware implementation and use
#356CONDUCTIVE FILM, DISPLAY DEVICE EQUIPPED WITH SAME, AND METHOD FOR DETERMINING PATTERN OF CONDUCTIVE FILM
#357Automated bottom-up and top-down partitioned design synthesis
#358Method for adjusting target layout based on intensity of background light in etch mask layer
#359Designing a folded sheet object
#360Geometric modeling with mutually dependent blends
#361Partitioning designs to facilitate certification
#362Curves in a variational system
#363Computer-implemented system and method for determining spatial locations of fixture element fixturing points on a part to be manufactured
#364Automatic synthesis of complex clock systems
#365High performance design rule checking technique
#366Method and system for designing and producing a user-defined toy construction element
#367Methods for orienting material physical properties using constraint transformation and isoparametric shape functions
#368Determining feasible splines with engineering constraints using projection methods
#369Product visualization
#370Method for creating personalized functional objects, computer, computer readable medium and computer program related thereto
#371Installation guide system for air conditioner and method of using the same
#372Setting method and information processing apparatus
#373System and method for computational planning in a data-dependent constraint management system
#374Method of fast analog layout migration
#375Box-based architectural design
#376Variational modeling with removal features
#377Integrating discovered and user-defined geometric relationships
#378Identification and management of redundancy within geometric relationships
#379Ordering optional constraints in a variational system
#380Blend behavior in a variational system
#381Push—shove layout route changing method using movement track of figure, computer-readable recording medium recording push—shove layout route changing program using movement track of figure and push—shove layout route changing system using movement track of figure
#382Symmetry of discovered geometric relationships in a three dimensional model
#383Representation and discovery of geometric relationships in a three dimensional model
#384Method and system for designing an assembly of objects in a system of computer-aided design
#385Automatically creating and modifying furniture layouts in design software
#386Method for changing string arrangement, recording medium for string arrangement changing program, and information processor
#387Semi-autonomous digital human posturing
#388Graph based degree of freedom counter for two dimensional drawings
#389Solving networks of geometric constraints
#390Constraint satisfaction problem solving using constraint semantics
#391Computer aided design model analysis system
#392Installation optimisation
#393Information integrating apparatus, method, and computer product
#394Techniques for optimizing stringing of solar panel modules
#395Designing a three-dimensional modeled assembly of objects in a three-dimensional scene
#396User interfaces for designing objects
#397Efficiently determining Boolean satisfiability with lazy constraints
#398Optimizing constraint solving by rewriting at least one modulo constraint
#399Manufacture of heat trace cable, design, installation, and management, and method thereof
#400Developing programs for hardware implementation in a graphical specification and constraint language
#401System and method for identifying under-defined geometries due to singular constraint schemes
#402Methods and system for modifying parameters of three dimensional objects subject to physics simulation and assembly
#403Method, computer program product and apparatus for providing a building options configurator
#404Computer method and apparatus for creating sketch geometry
#405Modeling dynamic systems by visualizing and narrowing a parameter space
#406Process of updating a status of relation between objects in a system of computer-aided design of objects
#407CAD system and method for wireframe coupling
#408Systems and methods for component-based architecture design
#409Assembly connection method for attaching virtual parts in a computer aided design software environment
#410System and method for modifying geometric relationships in a solid model
#411System and method for active selection in a solid model
#412Crashworthiness design methodology using a hybrid cellular automata algorithm for the synthesis of topologies for structures subject to nonlinear transient loading
#413Coil optimization for magnetic stimulation
#414Method for generating regular elements in a computer-aided design drawing
#415System and method for predicting human posture using a rules-based sequential approach
#416TCAD design template for fast prototyping of 2D and 3D CMOS image sensors
#417Modeling of sequential circuit devices of multi-clock domain IC design for a transient vectorless power analysis
#418Incremental synthesis for changes to a circuit design
#419Method and system for verification using combined verification data
#420Systems and methods for streaming waveform data during emulation run
#421System, method, and computer program product for computing formal coverage data compatible with dynamic verification
#422Tree-routing for specific areas of an electronic design
#423EM-compliance topology in a tree router
#424Systems and methods for dynamically generating hierarchical rotating pcells from a static integrated circuit design
#425Arrangement and method for facilitating electronics design in connection with 3D structures
#426Arrangement and method for facilitating electronics design in connection with 3D structures
#427Physical synthesis for multi-die integrated circuit technology
#428Multimode circuit place and route optimization
#429Routing framework to resolve single-entry constraint violations for integrated circuit designs
#430Integrated circuit routing based on enhanced topology
#431Systems and methods for estimating the future electrical resistance of a wire of a partially routed net
#432Systems and methods for routing a clock net with multiple layer ranges
#433Placement, routing, and deadlock removal for network-on-chip using integer linear programming
#434Routing circuit designs for implementation using a programmable network on chip
#435Method, system, and computer program product for implementing routing aware placement or floor planning for an electronic design
#436Incremental routing for circuit designs using a SAT router
#437Timing closure of circuit designs for integrated circuits
#438System, method, and computer program product for debugging in an electronic design file
#439Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design
#440Method, system, and computer program product for implementing routing aware placement for an electronic design
#441Systems and methods for reuse of delay calculation in static timing analysis
#442Analog design tool, cell set, and related methods, systems and equipment
#443Flexible constraint integrated circuit implementation runs
#444Constructing multi-element features using a 3D CAD system
#445Generating and inserting metal and metal etch shapes in a layout to correct design rule errors
#446Determination of clock path delays and implementation of a circuit design
#447Generating a colored track pattern of non-uniform width from a sparse set of tracks
#448Method, system, and computer program product for implementing legal placement with contextual awareness for an electronic design
#449Method, system, and computer program product for implementing group legal placement on rows and grids for an electronic design
#450Method and apparatus for performing fast incremental physical design optimization
#451Programmable logic device design implementations with multiplexer transformations
#452System, method, and computer program product for analyzing formal constraint conflicts
#453Methods for minimizing logic overlap on integrated circuits
#454Systems and methods for designing an integrated circuit
#455Method and apparatus for design rules driven interactive violation display
#456Methods, systems, and computer program product for implementing deadlock detection with formal verification techniques in an electronic design
#457Constraint based bit-stream compression in hardware for programmable devices
#458Direct probing characterization vehicle for transistor, capacitor and resistor testing
#459Systems and methods for finite difference time domain simulation of an electronic design
#460System and method for displaying routing options in an electronic design
#461Method and system to perform performance checks
#462Method and system to perform equivalency checks
#4632.5D electronic package
#464SRAM cell layout structure and devices therefrom
#465Techniques for optimizing dual track routing
#466Methods, systems, and articles of manufacture for implementing clone design components in an electronic design
#467Integrated circuits with interconnect selection circuitry
#468Integrated circuit floorplan having feedthrough buffers
#469Hierarchical preset and rule based configuration of a system-on-chip
#470Combining logic elements into pairs in a circuit design system
#471Verification of fractured mask data