191651 ⎘
FEOL interconnect used as capacitance over fins instead of gates
#2Automated Analysis of Mechanical Designs
#3Inertia scaling based on neighboring bodies
#4Minimization function for friction solving
#5Pre-characterization mixed-signal design, placement, and routing using machine learning
#6System and method for construction cost estimation for non-computer aided design (CAD) files
#7Method and system for part design using heterogeneous constraints
#8Net routing for integrated circuit (IC) design
#9Orientation optimization in components fabricated with anisotropic material properties
#10Multi-cycle latch tree synthesis
#11Timing model, timing model building method, and related top-level analysis method
#12Device/health of line (HOL) aware eBeam based overlay (EBO OVL) structure
#13Method and system for circuiting in heat exchangers
#14Distributed attitude control system for reconfigurable spacecraft composed of joined entities with compliant coupling
#15Method and system for automated design and design-space exploration
#16Method and system for hierarchical multi-scale part design with the aid of a digital computer
#17Computer-Implemented Method Of Estimating A Mass Distribution Of A Physical Product
#18Managing feedthrough wiring for integrated circuits
#19Propagating constants of structured soft blocks while preserving the relative placement structure
#20Pin access hybrid cell height design
#21Method to map convolutional layers of deep neural network on a plurality of processing elements with SIMD execution units, private memories, and connected as a 2D systolic processor array
#22Buffer-bay placement in an integrated circuit
#23Application- or algorithm-specific quantum circuit design
#24Semiconductor process modeling to enable skip via in place and route flow
#25Semiconductor process modeling to enable skip via in place and route flow
#26Semiconductor process modeling to enable skip via in place and route flow
#27Constrained cell placement
#28Providing Real-Time Predictive Feedback During Logic Design
#29Method for improved cut metal patterning
#30Systems and methods for SMT processes using uninterpreted function symbols
#31Optimizing level-set structural design of flexure mechanism
#32Method, computer program product and apparatus for providing a building options configurator
#33Smart placement, visualization and optimization methodology for component placement and planning
#34Methods and apparatuses to produce fluid control device components and related fluid control devices
#35Method for automatic detection of a functional primitive in a model of a hardware system
#36Less-pessimistic static timing analysis for synchronous circuits
#37Integrated circuit design model splitting for formal verification
#38Designing a 3D modeled object representing a mechanical structure
#39Method and system of revising a layout diagram
#40Optimizing library cells with wiring in metallization layers
#41Systems and methods for inter-die block level design
#42Integrated circuit (IC) design systems and methods using single-pin imaginary devices
#43System and method for a hybrid current-mode and voltage-mode integrated circuit
#44Pre-step co-simulation method and device
#45Method and system for designing a distributed heterogeneous computing and control system
#46Method and system for multiple views computer-aided-design including propagation of edit operations across views while ensuring constraints consistency
#47Method for selecting wave height threshold
#48Integrated circuit design system and method
#49Reliability robust design method for multiple failure modes of ultra-deep well hoisting container
#50Semiconductor process modeling to enable skip via in place and route flow
#51Systems and methods for customization of objects in additive manufacturing
#52Constructing flexible space-filling designs for computer experiments
#53Voltage drop assisted power-grid augmentation
#54Modifying circuits based on timing reports for critical paths
#55Incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield
#56System and method for fixture form-closure determination for part manufacturing with the aid of a digital computer
#57Automated accurate viable solar area determination
#58Multi-tier co-placement for integrated circuitry
#59Method and assembly for forming a building element
#60Automatic airfoil and wing design based on dynamic modeling of structural and aerodynamic performance
#61Resistance-based memory compiler
#62Symbiotic modeling system and method
#63Simplifying designs of mechanical assemblies via generative component consolidation
#64Method for fabricating a physical simulation device, simulation device and simulation system
#65Integrated circuit design
#66ACCURATE ESTIMATION OF UPPER ATMOSPHERIC DENSITY USING SATELLITE OBSERVATIONS
#67Computer executing method, clock data processing system and computer readable storage medium
#68Calibration of directed self-assembly models using programmed defects of varying topology
#69Methods for combinatorial constraint in topology optimization using shape transformation
#70Methods for topology optimization using a membership variable
#71Slack time recycling
#72Constraint-oriented programming approach to mechanical assembly design
#73Circuit design method and associated computer program product
#74Triple and quad coloring of shape layouts
#75Supervised automatic roof modeling
#76A DESIGN OPTIMIZATION METHOD FOR PREVENTING WRINKLING OF STRETCHED MEMBRANE STRUCTURES
#77Integrated circuit structure
#78Systems and methods for top level integrated circuit design
#79Integrated device and method of forming the same
#80Wirelength distribution schemes and techniques
#81Enabling automatic staging for nets or net groups with VHDL attributes
#82Tread pattern generation method for generating tread pattern of tire to reduce noise with higher precision
#83Hybrid method of assessing and predicting athletic performance
#84COMPUTER-IMPLEMENTED SYNTHESIS OF A MECHANICAL STRUCTURE USING A DIVERGENT SEARCH ALGORITHM IN CONJUNCTION WITH A CONVERGENT SEARCH ALGORITHM
#85Automatic assembly mate creation for frequently-used components
#86Variant cell height integrated circuit design
#87Efficient mechanism for interactive fault analysis in formal verification environment
#88Techniques for automatically generating designs having characteristic topologies for urban design projects
#89Techniques for automatically analyzing competing design objectives when generating designs for urban design projects
#90Generative design pipeline for urban and neighborhood planning
#91Growth-Based Design System
#923D tolerance analysis system and methods
#93Methods for automated hardware system synthesis
#94Integrated circuit layout methods, structures, and systems
#95Integrated circuit with peek and poke protection circuitry for a multi-tenant usage model
#96SYSTEMS AND METHODS FOR MEASURING ERROR IN TERMS OF UNIT IN LAST PLACE
#97Method for resisting dynamic load in high temperature pipeline
#98CONCURRENTLY OPTIMIZED SYSTEM-ON-CHIP IMPLEMENTATION WITH AUTOMATIC SYNTHESIS AND INTEGRATION
#99DESIGN-INFORMATION PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER READABLE MEDIUM
#100Integration method for accurate modeling and analysis and reliability-based design optimization of variable stiffness composite plate and shell structures
#101Method, system, and storage medium for engineering change order scheme in circuit design
#102Support apparatus and design support method
#103Standard cells and variations thereof within a standard cell library
#104Alignment key design rule check for correct placement of abutting cells in an integrated circuit
#105Method and apparatus for performing synthesis for field programmable gate array embedded feature placement
#106Method for rigidity enhancement and weight reduction using laser peening
#107Partitioning in post-layout circuit simulation
#108GENERATIVE SPACE PLANNING IN ARCHITECTURAL DESIGN FOR EFFICIENT DESIGN SPACE EXPLORATION
#109GENERATIVE SPACE PLANNING IN ARCHITECTURAL DESIGN FOR EFFICIENT DESIGN SPACE EXPLORATION
#110Customizable microfluidic device with programmable microfluidic nodes
#111System, method and computer product for enhanced decoupling capacitor implementation
#112Method to automatically generate and promote timing constraints in a Synopsys Design Constraint format
#113Adding constraints between components of a computer-aided design (CAD) model
#114Three-Dimensional Cad System Device, and Knowledge Management Method Used in Three-Dimensional Cad
#115SDA Collaboration
#116Data processing system and method for assembling components in a computer-aided design (CAD) environment
#117Verification support apparatus and design verification support method
#118Method for compression of emulation time line in presence of dynamic re-programming of clocks
#119Constrained cell placement
#120Method and system for overlay control
#121Field-effect transistor placement optimization for improved leaf cell routability
#122Field-effect transistor placement optimization for improved leaf cell routability
#123Prediction of process-sensitive geometries with machine learning
#124Systems and methods for layout objects selection and replication via a graphic-based layout editor
#125SYSTEMS AND METHODS FOR SELECTION AND OPERATION ON MULTIPLE GROUPS OF LAYOUT OBJECTS VIA A GRAPHIC-BASED LAYOUT EDITOR
#126Learning an autoencoder
#127Computer-implemented method and computing system for designing integrated circuit by considering timing delay
#128Pattern centric process control
#129SYSTEM AND METHOD FOR MODELING STAIRS
#130Techniques for optimizing dual track routing
#131DESIGN METHOD FOR CHOOSING SPECTRAL SELECTIVITY IN MULTISPECTRAL AND HYPERSPECTRAL SYSTEMS
#132Method and system for designing and producing a user-defined toy construction element
#133Method to synthesize a cross bar switch in a highly congested environment
#134Device and method for detecting points of failures
#135Example-based ranking techniques for exploring design spaces
#136INTEGRATED CIRCUIT LAYOUT DESIGN METHODOLOGY WITH PROCESS VARIATION BANDS
#137Technique for distributing routing into superfluous metal section of an integrated circuit
#138Method, design program, and design apparatus of a high level synthesis process of a circuit
#139Maintaining computational flow in a data-dependent constraint network
#140Data processing system to implement wiring/silicon blockages via parameterized cells
#141METHODS AND SYSTEMS FOR TIMING CONSTRAINT GENERATION IN IP/SoC DESIGN
#142Automatic timing-sensitive circuit extraction
#143Power grid insertion technique
#144Apparatus and method for range measurement
#145Electromigration check in layout design using compiled rules library
#146Techniques for statistical frequency enhancement of statically timed designs
#147METHODS AND SYSTEMS FOR IMPROVING USER EXPERIENCE OF AN ELECTRONIC DEVICE
#148Three-dimensional NoC reliability evaluation
#149VIRTUAL SENSOR FOR VIRTUAL ASSET
#150Architecture generating device
#151Conductive film, display device equipped with same, and method for determining pattern of conductive film
#152Concurrently optimized system-on-chip implementation with automatic synthesis and integration
#153Replica selection
#154Automatic partitioning of a 3D scene into a plurality of zones processed by a computing resource
#155A METHOD AND APPARATUS FOR PERFORMING A MODEL-BASED FAILURE ANALYSIS OF A COMPLEX INDUSTRIAL SYSTEM
#156Constructing multi-element features using a 3D CAD system
#157System and method for designing, receiving order of, and placing production-order of custom-made furniture and program therefor
#158Method to protect an IC layout
#159FINITE ELEMENT SIMULATION DEVICE AND METHOD FOR CAR BODY LOCAL STRUCTURE INSTABILITY OF HIGH-SPEED MOTOR TRAIN UNIT
#160System and method for assigning color pattern
#161Timing based net constraints tagging with zero wire load validation
#162Layout for semiconductor device including via pillar structure
#163Method and computer program for determining a placement of at least one circuit for a reconfigurable logic device
#164Target optimization method for improving lithography printability
#165Programmable logic integrated circuit, design support system, and configuration method
#166SIDE-BY-SIDE INTERACTIVE CIRCUIT DESIGN PANEL
#167Method for layout generation with constrained hypergraph partitioning
#168Resistance-based memory compiler
#169Method for manufacturing a spectacle frame adapted to a spectacle wearer
#170Triple and quad coloring of shape layouts
#171Triple and quad coloring shape layouts
#172Methods for verifying retimed circuits with delayed initialization
#173Support method, and information processing apparatus
#174Analog centric current modeling within a digital testbench in mixed-signal verification
#175Critical path straightening system based on free-space aware and timing driven incremental placement
#176DEVICE DESIGN RECEIVING SYSTEM
#177Neural Network Based Prediction of PCB Glass Weave Induced Skew
#178Automation generation of test layouts for verifying a DRC deck
#179Dynamic frequency boosting exploiting path delay variability in integrated circuits
#180Integrated circuit design using generation and instantiation of circuit stencils
#181Circuit design analyzer
#182Method for transistor design with considerations of process, voltage and temperature variations
#183Glitch-aware phase algebra for clock analysis
#184Spatial constraint based triangular mesh operations in three dimensions
#185Method for optimizing the design of micro-fluidic devices
#186Reuse of extracted layout-dependent effects for circuit design using circuit stencils
#187Circuit design support apparatus, circuit design support method, and computer readable medium
#188Component design system for generating aircraft component designs
#189ASIC design methodology for converting RTL HDL to a light netlist
#190Sharing global route topologies in detailed routing
#191Use of net-based target congestion ratios in global routing
#192Asynchronous pipeline circuit
#193Systems and methods for automatic determination of layout constraints
#194Method for verifying a layout designed for a semiconductor integrated circuit and a computer system for performing the same
#195System and method for determining spatial locations of fixture element fixturing points on a part to be manufactured with the aid of a digital computer
#196Method and apparatus for implementing a system-level design tool for design planning and architecture exploration
#197METHODS AND APPARATUS FOR A COIL DESIGNER
#198Systems and methods for optimizing component placement in a battery design
#199METHOD, SYSTEM AND PROGRAM PRODUCT FOR SADP-FRIENDLY INTERCONNECT STRUCTURE TRACK GENERATION
#200Method for optimizing the design of micro-fluidic devices
#201Optimal well placement under constraints
#202Printed circuit board design for manufacturing across multiple suppliers
#203Method and system for verifying layout of integrated circuit including vertical memory cells
#204System and method for solving and enforcing associative constraints
#205Integrated circuit design using generation and instantiation of circuit stencils
#206Reuse of extracted layout-dependent effects for circuit design using circuit stencils
#207Designing and fabricating semiconductor devices with specific terrestrial cosmic ray (TCR) ratings
#208Method wherein test cells and dummy cells are included into a layout of an integrated circuit
#209Identifying bugs in a counter using formal
#210Methods and systems for searching computer-aided design data
#211System and method for rapid and robust uncertainty management during multidisciplinary analysis
#212System and method for rapid and robust uncertainty management during multidisciplinary analysis
#213Distributed clash and snapping
#214Multilevel via placement with improved yield in dual damascene interconnection
#215Restricted region transform method and restricted region transform device
#216Static timing analysis in circuit design
#217Cell circuit and layout with linear finfet structures
#218Multiple patterning layout decomposition considering complex coloring rules
#219DESIGN SUPPORT DEVICE, METHOD, AND PROGRAM RECORD MEDIUM
#220Method and device for chip integration and storage medium
#221ARCHITECTURE AND DESIGN AUTOMATION OF HIGH PERFORMANCE LARGE ADDERS AND COUNTERS ON FPGA THROUGH CONSTRAINED PLACEMENT
#222METHOD AND SYSTEM FOR DETERMINING A CONFIGURATION OF A MODEL HAVING A COLLECTION OF ENTITIES AND SATISFYING A SET OF CONSTRAINTS
#223Layout optimization of a main pattern and a cut pattern
#224Timing exact design conversions from FPGA to ASIC
#225Methods for orienting material physical properties using constraint transformation and isoparametric shape functions
#226Network logic synthesis
#227Vanishable logic to enhance circuit security
#228Rule based completion of maps with partial data
#229Manufacturing method for a semiconductor device, pattern generating method and nontransitory computer readable medium storing a pattern generating program
#230Automated accurate viable solar area determination
#231Cross-hierarchy interconnect adjustment for power recovery
#232Alternative hierarchical views of a circuit design
#233Timing constraints formulation for highly replicated design modules
#234System and method for distributing multiple layers of a composite within a structural volume containing an inclusion
#235Synthesis tuning system for VLSI design optimization
#236Method for determining the parameters of an IC manufacturing process by a differential procedure
#237Via placement within an integrated circuit
#238Timing constraints formulation for highly replicated design modules
#239MODEL-BASED RULE TABLE GENERATION
#240Systems and methods for group constraints in an integrated circuit layout
#241Reciprocal quantum logic (RQL) circuit synthesis
#242System and method for designing, receiving order of, and placing production-order of custom-made furniture and program therefor
#243Polygon-based geometry classification for semiconductor mask inspection
#244Method and apparatus for implementing a system-level design tool for design planning and architecture exploration
#245Systems and methods for customization of objects in additive manufacturing
#246Methods of generating integrated circuit layout using standard cell library
#247USER INTERFACES FOR DESIGNING OBJECTS
#248Integrated circuit layout design methodology with process variation bands
#249Scaling of Integrated Circuit Design Including High-Level Logic Components
#250Method and apparatus for automatically assembling components in a computer-aided design (CAD) environment
#251SYSTEM AND METHOD FOR COMPUTATIONAL PLANNINGIN A DATA-DEPENDENT CONSTRAINT MANAGEMENT SYSTEM
#252Method, computer program product and apparatus for providing a building options configurator
#253Arrayed imaging systems having improved alignment and associated methods
#254Graphical specification and constraint language for developing programs for hardware implementation and use
#255Deadlock detection in hardware design using assertion based verification
#256Methods for designing and manufacturing transformers
#257System, method and computer-accessible medium for security-centric electronic system design
#258Collaborative generation of configuration technical data for a product to be manufactured
#259Method of design and manufacturing of aircraft structural object
#260Semiconductor device design methods and conductive bump pattern enhancement methods
#261Die including a high voltage capacitor
#262Multi-user cloud parametric feature-based 3D CAD system
#263Method for representing and generating a flat pattern for a composite ply that folds over itself
#264Calculating circuit-level leakage using three dimensional technology computer aided design and a reduced number of transistors
#265Method, computer program product and apparatus for providing a building options configurator
#266Simulation of resizable bodies using a rigid body solver
#267Device placement automatic calculation apparatus
#268Rule-based constraint interaction in geometric models
#269Methods, apparatus, and system for using filler cells in design of integrated circuit devices
#270Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout
#271Conditional phase algebra for clock analysis
#272Method of decomposing layout of semiconductor device for quadruple patterning technology process and method of manufacturing semiconductor device using the same
#273System for designing network on chip interconnect arrangements
#274Associating computer-executable objects with three-dimensional spaces within an architectural design environment
#275MEMORY REDUNDANCY REDUCTION
#276System for and method of checking joule heating of an integrated circuit design
#277Integrated circuit and routing design of the same
#278Methods of generating integrated circuit layout using standard cell library
#279System, method, apparatus, and computer program product for generation of an elevation plan for a computing system
#280Method of converting between non-volatile memory technologies and system for implementing the method
#281Optimizing constraint solving by rewriting at least one bit-slice constraint
#282MEMS modeling system and method
#283Variation modeling
#284Clock-gating phase algebra for clock analysis
#285Circuit design analyzer
#286EDA tool and method for conflict detection during multi-patterning lithography
#287Generating a semiconductor component layout
#288Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management
#289System and method for reducing power of a circuit using critical signal analysis
#290Cell-level signal electromigration
#291System design management
#292System design management
#293System design management
#294Product intelligence engine
#295Method for high-frequency amplifier using power gain-boosting technique
#296Insulation distance check device
#297Product configuration
#298PRINTED CIRCUIT BOARD DESIGN VERIFICATION SYSTEM, PRINTED CIRCUIT BOARD DESIGN VERIFICATION METHOD, AND RECORDING MEDIUM
#299System and method for designing and validating computing systems
#300Transformer with improved power handling capacity