Method of fabricating an integrated circuit with optimized pattern density uniformity

System and method for integrated circuit manufacturing

Stretch dummy cell insertion in finFET process

ESD protection circuit cell

Automated design and manufacturing feedback for three dimensional (3D) printability

Automated metrology and model correction for three dimensional (3D) printability

Method and system for overlay control

Transformer synthesis and optimization in integrated circuit design

Shared channel masks in on-product test compression system

Shared channel masks in on-product test compression system

Dynamic yield prediction

Method for printing three-dimensional parts with part strain orientation

Minimizing harmful effects caused by reticle defects by re-arranging IC layout locally

Synthesizing low mask error enhancement factor lithography solutions

Generating guiding patterns for directed self-assembly

Method and apparatus for controlling printability of a 3-dimensional model

Common template for electronic article

Invariant sharing to speed up formal verification

Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout

Placing transistors in proximity to through-silicon vias

Layout design system for generating layout design of semiconductor device

Layout optimization for integrated circuit design

Area array device connection structures with complimentary warp characteristics

Method for generating layout of photomask

Methods of patterning wafers using self-aligned double patterning processes

Method for creating three dimensional lattice structures in computer-aided design models for additive manufacturing

Method to improve transistor matching

System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks

Performance-driven and gradient-aware dummy insertion for gradient-sensitive array

Method of designing impedance transformation circuit

WEAK POINTS AUTO-CORRECTION PROCESS FOR OPC TAPE-OUT

Pattern-based via redundancy insertion

Method of making semiconductor device and system for performing the same

Techniques for optimizing orientation of models for three-dimensional printing

Techniques for performing cross-sectional stress analysis for three-dimensional objects

Generating support material for three-dimensional printing

Generating support material for three-dimensional printing

Simulation method, simulation program, process control system, simulator, process design method, and mask design method

Layout design for electron-beam high volume manufacturing

Methods for cell phasing and placement in dynamic array architecture and implementation of the same

Determination Of Electromigration Features

Grouping layout features for directed self assembly

Three-dimensional object development

Canonical forms of layout patterns

Method and system for repairing wafer defects

Method for implementing design-for-manufacturability checks

System and method for CNC machines and software

Method of determining if layout design is N-colorable

Chip level critical point analysis with manufacturer specific data

Method of making semiconductor device and a control system for performing the same

METHOD, PROGRAM PRODUCT AND APPARATUS FOR PERFORMING DOUBLE EXPOSURE LITHOGRAPHY

Method and system for multi-patterning layout decomposition

Rule and lithographic process co-optimization

Hierarchical Approach to Triple Patterning Decomposition

Modeling multi-patterning variability with statistical timing

Layout optimization for integrated circuit design

Method for forming circular patterns on a surface

Optimization of source, mask and projection optics

Layout content analysis for source mask optimization acceleration

Integrated circuit layout design methodology with process variation bands

Method and system for overlay control

EVALUATION SAMPLE, METHOD OF OBTAINING ETCHING YIELD FUNCTION AND SIMULATION METHOD

Detecting and displaying multi-patterning fix guidance

Mask design and decomposition for sidewall image transfer

Scaling of bipolar transistors

Method for manufacturing EUV masks minimizing the impact of substrate defects

Graphical specification and constraint language for developing programs for hardware implementation and use

Method and system for design of a reticle to be manufactured using variable shaped beam lithography

Method for adjusting target layout based on intensity of background light in etch mask layer

Method and apparatus for a diffusion bridged cell library

Verification support method, recording medium having stored verification support program therein, and verification support apparatus

Device for assisting with setting of manufacturing conditions for silica glass crucible, device for assisting with setting of manufacturing conditions for mold for manufacturing silica glass crucible, device for assisting with condition setting for pulling up monocrystalline silicon using silica glass crucible

Information processing apparatus, information processing method, program, and board manufacturing system

MODULAR PLATFORM FOR INTEGRATED CIRCUIT DESIGN ANALYSIS AND VERIFICATION

Semiconductor device and method for making the same using semiconductor fin density design rules

Stretch dummy cell insertion in FinFET process

Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods

Method of performing circuit simulation and generating circuit layout

Common template for electronic article

Topography driven OPC and lithography flow

Method and apparatus for performing optical proximity and photomask correction

Design-for-manufacturing—design-enabled-manufacturing (DFM-DEM) proactive integrated manufacturing flow

Area array device connection structures with complimentary warp characteristics

Integrated circuit device, method for producing mask layout, and program for producing mask layout

Semiconductor chip including integrated circuit defined within dynamic array section

Variation factor assignment

Double-mask photolithography method minimizing the impact of substrate defects

Layout decomposition for triple patterning lithography

Layout method and system for multi-patterning integrated circuits

Method and system for forming high accuracy patterns using charged particle beam lithography

Arrayed imaging systems having improved alignment and associated methods

Adjustable dummy fill

Method and system for designing 3D semiconductor package

Pre-colored methodology of multiple patterning

Enforcement of semiconductor structure regularity for localized transistors and interconnect

Method and system for identifying fastener placement zones

Performance-driven and gradient-aware dummy insertion for gradient-sensitive array

Lithography aware leakage analysis

Placing transistors in proximity to through-silicon vias

System and method for critical path replication

Fragmentation point and simulation site adjustment for resolution enhancement techniques

Setting method and information processing apparatus

Object design data model

Compensation for patterning device deformation

Layout method for printed circuit board

Systems and methods for integrated circuit C4 ball placement

Nesting using rigid body simulation

Pre-colored methodology of multiple patterning

Methodology on developing metal fill as library device

Compression method and system for use with multi-patterning

Fabrication of materials with desired characteristics from base materials having determined characteristics

Semiconductor structure and method for fabricating semiconductor layout

Dummy patterns and method for generating dummy patterns

Dummy patterns and method for generating dummy patterns

Low-voltage swing circuit modifications

Methods for cell phasing and placement in dynamic array architecture and implementation of the same

Method of decomposing layout of semiconductor device

Pattern-dependent proximity matching/tuning including light manipulation by projection optics

Cross-coupling based design using diffusion contact structures

Soft error and radiation hardened sequential logic cell

Method for creating a photolithography mask

Microelectromechanical system design and layout

Method and system for design of a reticle to be manufactured using variable shaped beam lithography

Method of managing electro migration in logic designs and design structure thereof

System and method for lithography simulation

Modified design rules to improve device performance

Semiconductor device design system and method of using the same

Systems and methods for creating frequency-dependent netlist

Analysis optimizer

Mobile applicator for thermo pavement marking

Method for increasing the robustness of a double patterning router used to manufacture integrated circuit devices

Process aware metrology

Method and apparatus for optimizing refrigeration systems

Structure and method for E-beam writing

Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires

Dummy gate cell, cell-based IC, and portable device

Generating capacitance look-up tables for wiring patterns in the presence of metal fills

Generation method, storage medium, and information processing apparatus

Supporting device, design support method and computer-readable recording medium

Rapid prototyping process and device using parallel computation for working points

Circuit assembly yield prediction with respect to manufacturing process

Processor for executing wide operand operations using a control register and a results register

ESD protection circuit cell

Semiconductor device and layout design method for the same

Circuits with linear finfet structures

Parameter matching hotspot detection

Method for checking and fixing double-patterning layout

Layout content analysis for source mask optimization acceleration

Metal density aware signal routing

Method and apparatus to enable a selective push process during manufacturing to improve performance of a selected circuit of an integrated circuit

Robust design using manufacturability models

Method and system for automatic generation of solutions for circuit design rule violations

Lens and method of forming shape of lens based on calculated normal direction of light incident points on virtual light incident surface

Developing programs for hardware implementation in a graphical specification and constraint language

Semiconductor integrating circuit layout pattern generating apparatus and method

Simulation parameter correction technique

Simultaneous multi-layer fill generation

Scaling of bipolar transistors

Integrated circuit device with reduced leakage and method therefor

Optimizing bias points for a semiconductor device

Dummy pattern performance aware analysis and implementation

Adjustable dummy fill

Cell circuit and layout with linear finfet structures

Integrated circuit having adaptive via sizing

Methods for controlling microloading variation in semiconductor wafer layout and fabrication

Integrated design-for-manufacturing platform

Method and system for automatically extracting layout design patterns for custom layout design reuse through interactive recommendations

Calculating and extracting joule-heating and self-heat induced temperature on wire segments for chip reliability

Tree-routing for specific areas of an electronic design

EM-compliance topology in a tree router

Arrangement and method for facilitating electronics design in connection with 3D structures

Digital device protective artwork case method and device

Serial pixel processing with storage for overlapping texel data

Light source and method for making a light source

Interactive platform to predict mismatch variation and contribution when adjusting component parameters

Integrated circuit simulation with data persistency for efficient memory usage

Integrated circuit simulation with efficient memory usage

Analog design tool, cell set, and related methods, systems and equipment

Timing optimization driven by statistical sensitivites

Direct probing characterization vehicle for transistor, capacitor and resistor testing

Method for manufacturing custom in-ear monitor with decorative faceplate

Methods, systems, and articles of manufacture for implementing a physical design of an electronic design with DFM and design specification awareness

Model-based definition for machining aircraft parts

Method and system for implementing efficient trim data representation for an electronic design

Breast shape visualization and modeling tool

Methods, systems, and articles of manufacture for implementing an electronic design with disconnected field domains

Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques

Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs

SRAM cell layout structure and devices therefrom

Method and system for creating improved routing polygon abstracts

Lithography mask functional optimization and spatial frequency analysis

Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control

Based device risk assessment

OPC method with higher degree of freedom

Optimized design verification of an electronic circuit

Computational thermal analysis during microchip design

Managing aging of silicon in an integrated circuit device