System and method for reducing power of a circuit using critical signal analysis

Clock skew adjusting structure

Congestion aware layer promotion

Congestion aware layer promotion

Apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium

Method and apparatus for calculating delay timing values for an integrated circuit design

Virtual sub-net based routing

Semiconductor arrangement formation

Virtual sub-net based routing

Timing violation resilient asynchronous template

Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits

Method and apparatus for calculating delay timing values for an integrated circuit design

System and method for efficient statistical timing analysis of cycle time independent tests

Designing photonic switching systems utilizing equalized drivers

Fast settling phase locked loop (PLL) with optimum spur reduction

Timing closure using transistor sizing in standard cells

Method and design apparatus

Method for layout design and structure with inter-layer vias

Phase algebra for analysis of hierarchical designs

Methods for static checking of asynchronous clock domain crossings

Method and apparatus for physical-aware hold violation fixing

System for partitioning integrated circuit design based on timing slack

Integrated circuit design timing path verification tool

Limiting skew between different device types to meet performance requirements of an integrated circuit

Partial parameters and projection thereof included within statistical timing analysis

Apportioning synthesis effort for better timing closure

Balancing sensitivities with respect to timing closure for integrated circuits

Determining soft error infliction probability

Circuit simulation using a recording of a reference execution

Time-variant temperature-based 2-D and 3-D wire routing

Detailed placement with search and repair

Tier based layer promotion and demotion

Boundary latch and logic placement to satisfy timing constraints

METHOD AND APPARATUS FOR TIMING VERIFICATION

Characterizing cell using input waveform generation considering different circuit topologies

System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks

System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells

System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks

Automatic pipelining of NoC channels to meet timing and/or performance

Timing delay characterization method, memory compiler and computer program product

Phase algebra for analysis of hierarchical designs

Aging-based leakage energy reduction method and system

Verification of asynchronous clock domain crossings

Circuit design evaluation with compact multi-waveform representations

Static checking of asynchronous clock domain crossings

Conditional phase algebra for clock analysis

Clock-gating phase algebra for clock analysis

Glitch-aware phase algebra for clock analysis

Method and apparatus for use in design of a system

Voltage droop mitigation in 3D chip system

Transport network

Efficient model for gate output slew computation in early synthesis

Apparatus and methods for partitioning an integrated circuit design into multiple programmable devices

Apparatus and methods for optimization of integrated circuits

Path-based floorplan analysis

Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems, methods and related components

Cell library and method for designing an asynchronous integrated circuit

Methods and tools for designing integrated circuits with auto-pipelining capabilities

Method and apparatus for simulating a digital circuit

Congestion estimation techniques at pre-synthesis stage

Register clustering for clock network topology generation

Chip level critical point analysis with manufacturer specific data

CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, CIRCUIT DESIGN SUPPORT APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT

Concurrent optimization of timing, area, and leakage power

Clock skew adjusting method and structure

Transmitting LSB timestamp datum in parallel and MSB in series

Modeling multi-patterning variability with statistical timing

User grey cell

TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM

Integrated circuit layout design methodology with process variation bands

Generalized moment based approach for variation aware timing analysis

VLSI layouts of fully connected generalized and pyramid networks with locality exploitation

Method for displaying timing information of an integrated circuit floorplan in real time

Dynamic control of design clock generation in emulation

Integrated circuit device configuration methods adapted to account for retiming

Clustering For Processing Of Circuit Design Data

Determining a set of timing paths for creating a circuit abstraction

Relative timing characterization

Systems and methods for reducing power consumption in semiconductor devices

Automated bottom-up and top-down partitioned design synthesis

Constraint memory node identification in sequential logic

Method for placing operational cells in a semiconductor device

Specifying and implementing relative hardware clocking in a high level programming language

Integrated circuit design verification through forced clock glitches

Timing operations in an IC with configurable circuits

SUPPORT DEVICE, DESIGN SUPPORT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM

Dual-structure clock tree synthesis (CTS)

Predictive 3-D virtual fabrication system and method

Timing delay characterization method, memory compiler and computer program product

Arrival edge usage in timing analysis

Synthesis of clock gated circuit

Finite-state machine encoding during design synthesis

Signal selection apparatus and system, and circuit emulator and method and program

Method and apparatus for timing closure

Interpolation techniques used for time alignment of multiple simulation models

Interpolation techniques used for time alignment of multiple simulation models

Timing bottleneck analysis across pipelines to guide optimization with useful skew

Semiconductor integrated circuit partitioning and timing

Modeling a bus for a system design incorporating one or more programmable processors

Automatic pipeline stage insertion

Structural rule analysis with TCL scripts in synthesis or STA tools and integrated circuit design tools

Transport network

Identification of mistimed forcing of values in design simulation

Electronic circuit design method

Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment

Propagation simulation buffer for clock domain crossing

Statistical corner evaluation for complex on-chip variation model

Optimized buffer placement based on timing and capacitance assertions

Generating pattern-based estimated RC data with analysis of route information

Predicting timing violations

Method and apparatus for monitoring timing of critical paths

Retiming a design for efficient parallel simulation

Display and automatic improvement of timing and area in a network-on-chip

RC extraction for single patterning spacer technique

Dynamically determining number of simulations required for characterizing intra-circuit incongruent variations

LSI design method

Macro timing analysis device, macro boundary path timing analysis method and macro boundary path timing analysis program

Clock-tree transformation in high-speed ASIC implementation

Modeling of cell delay change for electronic design automation

Efficient timing calculations in numerical sequential cell sizing and incremental slack margin propagation

Power balanced pipelines

Integrating manufacturing feedback into integrated circuit structure design

Magnetic force characteristic computing method, magnetic force characteristic computing device and computer program

Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data

Voltage drop effect on static timing analysis for multi-phase sequential circuit

Prediction of dynamic current waveform and spectrum in a semiconductor device

Automated circuit design

Gate substitution based system and method for integrated circuit power and timing optimization

Modeling output delay of a clocked storage element(s)

Hyper-concurrent optimization over multi-corner multi-mode scenarios

Common shared memory in a verification system

Global timing modeling within a local context

Device specific configuration of operating voltage

Methods and circuits for optimizing performance and power consumption in a design and circuit employing lower threshold voltage (LVT) devices

Automated system latency detection for fabric simulation

Computer product, IP model generating apparatus, and IP model generating method

Techniques for incorporating timing jitter and/or amplitude noise into hardware description language-based input stimuli

Selective conditional stall for hardware-based circuit design verification

Critical path aware voltage drop analysis of an integrated circuit

Physical synthesis within placement

Verifying equivalence of design latency

Modeling of sequential circuit devices of multi-clock domain IC design for a transient vectorless power analysis

Physical synthesis for multi-die integrated circuit technology

System, method, and computer program product for range-based clock analysis associated with the formal verification of an electronic circuit design

Multimode circuit place and route optimization

Circuit place and route optimization based on path-based timing analysis

Timer and content security

Region aware clustering

Local cluster refinement

Systems and methods for routing track assignment

Circuit design transformation for automatic latency reduction

Incremental routing for circuit designs using a SAT router

Systems and methods for modeling integrated clock gates activity for transient vectorless power analysis of an integrated circuit

Integrated circuit simulation with efficient memory usage

Methods for determining resistive-capacitive component design targets for radio-frequency circuitry

Methods for bounding the number of delayed reset clock cycles for retimed circuits

Timing optimization driven by statistical sensitivites

System and method for visualization and analysis of a chip view including multiple circuit design revisions

Generating clock trees for a circuit design

Overcoming retiming limitations due to initial conditions conflicts

Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact

Hierarchical timing analysis for multi-instance blocks

Methods for incremental circuit design legalization during physical synthesis

Method and apparatus for performing register retiming by utilizing native timing-driven constraints

Efficient techniques for process variation reduction for static timing analysis

Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs

Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design

Method and apparatus for performing a single pass compilation for systems with dynamically reconfigurable logic blocks

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Method and system for functional verification and power analysis of clock-gated integrated circuits

Automatic pipelining of NoC channels to meet timing and/or performance

Method and system for debugging a system on chip under test

High performance static timing analysis system and method for input/output interfaces

System and method for generating reduced standard delay format files for gate level simulation

Method and system for performing distributed timing signoff and optimization

Post-routing structural netlist optimization for circuit designs

Opportunistic candidate path selection during physical optimization of a circuit design for an IC

Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions

System and method of fast phase aligned local generation of clocks on multiple FPGA system

Method and system to perform performance checks

Systems and methods for estimating performance characteristics of hardware implementations of executable models

Register retiming and verification of an integrated circuit design

View data sharing for efficient multi-mode multi-corner timing analysis

Integrated circuits with interconnect selection circuitry

Methods, systems, and articles of manufacture for implementing scalable statistical library characterization for electronic designs

Testing critical paths of a circuit design

Method and system for reducing redundant logic in an integrated circuit

Method and system for calculating timing variations considering simultaneous switching noise

Method of designing fin-based transistor for power optimization

Circuit design technique for DQS enable/disable calibration

System and method for accurate modeling of back-miller effect in timing analysis of digital circuits

User-constrained delay redistribution

Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages

Methods, systems, and apparatus for clock topology planning with reduced power consumption

Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs

Timing budgeting of nested partitions for hierarchical integrated circuit designs

Timer analysis and identification