Efficient projection based adjustment evaluation in static timing analysis of integrated circuits

Modular event-based performance monitoring in integrated circuit development

Clock gating latch placement

Out-of-context feedback hierarchical large block synthesis (HLBS) optimization

Superconducting circuit with virtual timing elements and related methods

Sink-based wire tagging in multi-sink integrated circuit net

Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits

Deterministic test pattern generation for designs with timing exceptions

Hierarchical clock tree implementation

Apparatus and method for circuit timing fixing using extension metal sections and alternate vias

Hierarchical clock tree construction based on constraints

Selectively grounding fill wires

Automatic layer trait generation and promotion cost computation

Chip health monitor

System and method for compact neural network modeling of transistors

Multi-cycle latch tree synthesis

Embedded FPGA timing sign-off

Timing model, timing model building method, and related top-level analysis method

Characterization of spatial correlation in integrated circuit development

Apparatus and method of operating timing analysis considering multi-input switching

Variable accuracy incremental timing analysis

CONSTRUCTION OF STAGING TREES ON FULLY HIERARCHICAL VLSI CIRCUIT DESIGNS

Event-triggered analysis for high fidelity simulation

Methods of fabricating semiconductor devices, and related layout design systems

Propagating constants of structured soft blocks while preserving the relative placement structure

Testing system and testing method

Method for determining IC voltage and method for finding relation between voltages and circuit parameters

Method for generating aging model and manufacturing semiconductor chip using the same

Buffer-bay placement in an integrated circuit

Method and apparatus for transaction based propagated clock-gating for low power design

Static voltage drop (SIR) violation prediction systems and methods

Method of manufacturing devices

Elmore delay time (EDT)-based resistance model

Time-driven placement and/or cloning of components for an integrated circuit

Circuit testing and manufacture using multiple timing libraries

Application specific integrated circuit link

System and method for application specific integrated circuit design

Method and apparatus for relocating design modules while preserving timing closure

Less-pessimistic static timing analysis for synchronous circuits

Timing-adaptive, configurable logic architecture

Pessimism in static timing analysis

Reflection-canceling package trace design

Circuit module for modelling a digital circuit and simulation device including the circuit module

Method of regulating integrated circuit timing and power consumption

Systems and methods for inter-die block level design

Automated region based optimization of chip manufacture

Speed converter for FPGA-based UFS prototypes

Pessimism reduction in cross-talk noise determination used in integrated circuit design

Partial parameters and projection thereof included within statistical timing analysis

Method and system for forming conductive grid of integrated circuit

Circuit design system, checking method, and non-transitory computer readable medium thereof

Voltage drop assisted power-grid augmentation

Modifying circuits based on timing reports for critical paths

Model-building method for building top interface logic model

Scalable connectivity verification using conditional cut-points

System and method for predictive 3-D virtual fabrication

Leverage cycle stealing within optimization flows

System and method for performing a multi-etch process using material-specific behavioral parameters in a 3-D virtual fabrication environment

System and method of analyzing integrated circuit in consideration of a process variation and a shift

Phase algebra for virtual clock and mode extraction in hierarchical designs

Control path verification of hardware design for pipelined process

Computer executing method, clock data processing system and computer readable storage medium

Coupling aware wire capacitance adjust at global routing

Chip design method of optimizing circuit performance according to change in PVT operation conditions

Overcoming retiming limitations due to initial conditions conflicts

Machine-learning circuit optimization using quantized prediction functions

Slack time recycling

Leverage cycle stealing within optimization flows

Die resistance-capacitance extraction and validation

Interactive incremental synthesis flow for integrated circuit design

Parasitic extraction based on compact representation of process calibration data

Semiconductor process and performance sensor

Circuit design method and associated computer program product

Analyzing delay variations and transition time variations for electronic circuits

Timing based camouflage circuit

Memory element graph-based placement in integrated circuit design

Verifying sequential equivalence for randomly initialized designs

Distributed programmable delay lines in a clock tree

Constructing staging trees in hierarchical circuit designs

Placement and timing aware wire tagging

Enabling automatic staging for nets or net groups with VHDL attributes

Method of forming conductive grid of integrated circuit

Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks

System and method for application specific integrated circuit design

Reducing timing skew in a circuit path

Automatic multi-clock circuit generation

Integrated metal layer aware optimization of integrated circuit designs

Method and apparatus for relocating design modules while preserving timing closure

Die interface enabling 2.5D device-level static timing analysis

Method and apparatus for performing synthesis for field programmable gate array embedded feature placement

Method and apparatus for performing field programmable gate array packing with continuous carry chains

Formal clock network analysis, visualization, verification and generation

High-level synthesis device, high-level synthesis method, and program recording medium

Methods of manufacturing semiconductor devices by etching active fins using etching masks

Device for simulating multicore processors

Waveform based reconstruction for emulation

Reducing clock power consumption of a computer processor

Reducing clock power consumption of a computer processor

Reducing clock power consumption of a computer processor

Method for system level static power validation

Computer-implemented method and computing system for designing integrated circuit by considering process variations of wire

System, method and computer product for enhanced decoupling capacitor implementation

Method to automatically generate and promote timing constraints in a Synopsys Design Constraint format

Modifying a circuit design

Parameter collapsing and corner reduction in an integrated circuit

Parameter collapsing and corner reduction in an integrated circuit

Parameter collapsing and corner reduction in an integrated circuit

Circuit simulation using a recording of a reference execution

Multi-die IC layout methods with awareness of mix and match die integration

Verification support apparatus and design verification support method

Method for compression of emulation time line in presence of dynamic re-programming of clocks

Timer and content security

Dynamic microprocessor gate design tool for area/timing margin control

Method for simulating execution of an application on a multi-core processor

Integrated circuit including cells/gates arranged based on supply voltage variations of cells and influence between cells, and design method thereof

Computer-implemented method and computing system for designing integrated circuit by considering timing delay

Incremental register retiming of an integrated circuit design

Engineering change order aware global routing

Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit

INTEGRATED CIRCUIT LAYOUT DESIGN METHODOLOGY WITH PROCESS VARIATION BANDS

Structure and generation method of clock distribution network

Methods of manufacturing finFET semiconductor devices

Technique for distributing routing into superfluous metal section of an integrated circuit

Online monitoring unit and control circuit for ultra-wide voltage range applications

Method and system for sigma-based timing optimization

Method, design program, and design apparatus of a high level synthesis process of a circuit

Multi-sided variations for creating integrated circuits

Multi-sided variations for creating integrated circuits

Multi-sided variations for creating integrated circuits

Exact delay synthesis

Leverage cycle stealing within optimization flows

Leverage cycle stealing within optimization flows

Hard error simulation and usage thereof

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions

Method of timing analysis

Computer implemented methods and computing systems for designing integrated circuits by considering back-end-of-line

Neural cell and a neural network

Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library

Glitch detection at clock domain crossing

Method and apparatus for supporting temporal virtualization on a target device

Block-level design method for heterogeneous PG-structure cells

CIRCUIT DELAY ANALYZING APPARATUS, CIRCUIT DELAY ANALYZING METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM

Method to perform full accuracy hierarchical block level timing analysis with parameterized chip level contexts

Voltage and frequency balancing at nominal point

Voltage and frequency balancing at nominal point

Approximation of resistor-capacitor circuit extraction for thread-safe design changes

Neural network based physical synthesis for circuit designs

Architecture generating device

Method of tuning components within an integracted circuit device

Callback based constraint processing for clock domain independence

Circuit testing and manufacture using multiple timing libraries

Layout for semiconductor device including via pillar structure

Application specific integrated circuit link

Context-dependent useful skew estimation for optimization, placement, and clock tree synthesis

Clock jitter emulation

Placement-based congestion-aware logic restructuring

Optimized function assignment in a multi-core processor

Phase algebra for analysis of hierarchical designs

Methods for reducing delay on integrated circuits by identifying candidate placement locations in a leveled graph

Voltage and frequency balancing at nominal point

Integrating manufacturing feedback into integrated circuit structure design

Method of designing semiconductor device

Digital signal transition counters for digital integrated circuits

Circuit design analyzer

Integrated circuits having expandable processor memory

Accurate statistical timing for boundary gates of hierarchical timing models

Glitch-aware phase algebra for clock analysis

Dynamic power reduction in circuit designs and circuits

Critical path architect

Incremental parasitic extraction for coupled timing and power optimization

Programmable clock division methodology with in-context frequency checking

Hybrid out of context hierarchical design flow for hierarchical timing convergence of integrated circuits for out of context signoff analysis

Addressing of process and voltage points

Temperature-dependent printed circuit board trace analyzer

Methods and systems for managing memory blocks of semiconductor devices in embedded systems

Method and apparatus for improving system operation by replacing components for performing division during design compilation

Callback based constraint processing for clock domain independence

Integrated circuit design method and associated non-transitory computer-readable medium

Integrated circuit design verification

Detecting dispensable inverter chains in a circuit design

Timing analysis and optimization of asynchronous circuit designs

Optimizing the layout of circuits based on multiple design constraints

Verification of untimed nets

Dynamic microprocessor gate design tool for area/timing margin control

Clock tree synthesis based on computing critical clock latency probabilities

Methods and Computer-Readable Media for Synthesizing a Multi-Corner Mesh-Based Clock Distribution Network for Multi-Voltage Domain and Clock Meshes and Integrated Circuits

Method and system for functional verification and power analysis of clock-gated integrated circuits

Using deep sub-micron stress effects and proximity effects to create a high performance standard cell

System and Method for Optimization of Digital Circuits with Timing and Behavior Co-Designed by Introduction and Exploitation of False Paths

Systems and methods for using multiple libraries with different cell pre-coloring

Semiconductor integrated circuit having different operation modes and design method thereof

Method and apparatus for performing register retiming in the presence of timing analysis exceptions

Method for layout design and structure with inter-layer vias

Analyzing delay variations and transition time variations for electronic circuits

Distributed timing analysis of a partitioned integrated circuit design

METHODS AND SYSTEMS FOR FUNCTIONAL ANALYSIS OF AN INTEGRATED CIRCUIT

Method for analysis, analyzer, and non-transitory computer-readable recording medium having stored therein analysis program

Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design

Resource aware method for optimizing wires for slew, slack, or noise

Accurate statistical timing for boundary gates of hierarchical timing models

Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit

System and method for combined path tracing in static timing analysis

Adaptive characterization and instantiation of timing abstracts

Method and apparatus for adjusting a timing derate for static timing analysis

Incremental parasitic extraction for coupled timing and power optimization

Coupling aware wire capacitance adjust at global routing

Majority logic synthesis

Method for equipping registers of an integrated circuit to detect timing violations

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Static timing analysis in circuit design

Voltage droop mitigation in 3D chip system

Integration of functional analysis and common path pessimism removal in static timing analysis

Clock jitter emulation

2.5D electronic package

Timing adjustments across transparent latches to facilitate power reduction

Micro-benchmark analysis optimization for microprocessor designs

Application specific integrated circuit link

Level faults interception in integrated circuits

Hybrid out of context hierarchical design flow for hierarchical timing convergence of integrated circuits for out of context signoff analysis

Characterizing cell using input waveforms with different tail characteristics

Network logic synthesis

System and process for simulating the behavioral effects of timing violations between unrelated clocks

Waveform based reconstruction for emulation

Timing constraints formulation for highly replicated design modules

Integrated circuit chip design methods and systems using process window-aware timing analysis

Integrated circuit design

Contact resistance mitigation

Incremental register retiming of an integrated circuit design

TIMING WINDOW MANIPULATION FOR NOISE REDUCTION

Timing constraints formulation for highly replicated design modules

Timing constraints formulation for highly replicated design modules

Automatic pipelining of NoC channels to meet timing and/or performance

Aging-based leakage energy reduction method and system

Prioritized path tracing in statistical timing analysis of integrated circuits

Congestion aware layer promotion

Slack redistribution for additional power recovery

Slack redistribution for additional power recovery

Critical path architect

Designing apparatus for designing a programmable logic device, method of designing a programmable logic device and recording medium for storing a program for designing a programmable logic device

Hierarchical wire-pin co-optimization

Timing analysis method for digital circuit design and system thereof

Integrated circuit layout design methodology with process variation bands

Validating a clock tree delay

Look-ahead timing prediction for multi-instance module (MIM) engineering change order (ECO)

Dynamic and adaptive timing sensitivity during static timing analysis using look-up table

Adjustment and compensation of delays in photo sensor microcells

Method and apparatus for utilizing estimations for register retiming in a design compilation flow

Liberty file generation

Method of estimating a yield of an integrated circuit and method of optimizing a design for an integrated circuit

Methods for performing register retiming operations into synchronization regions interposed between circuits associated with different clock domains

Method for adjusting a timing derate for static timing analysis

Method and apparatus for automatic relative placement generation for clock trees

Iterative solution using compressed inductive matrix for efficient simulation of very-large scale circuits

Control path verification of hardware design for pipelined process

Signal integrity delay utilizing a window bump-based aggressor alignment scheme

Circuit layouts, methods and apparatus for arranging integrated circuits

Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness

System and method of analyzing integrated circuit in consideration of a process variation

Collapsing terms in statistical static timing analysis

Data propagation analysis for debugging a circuit design

Time domain response simulation system

Physical aware technology mapping in synthesis

Physical aware technology mapping in synthesis

Apparatus of wave-pipelined circuits

Systematic method of synthesizing wave-pipelined circuits in HDL

Systematic method of coding wave-pipelined circuits in HDL

System and method for performing directed self-assembly in a 3-D virtual fabrication environment

Method of performing static timing analysis for an integrated circuit

Computer implemented method for behavior analysis of an integrated circuit comprising paths selection based on an aggregation criterion and predefined analysis strategy

Subthreshold standard cell library

Phase algebra for virtual clock and mode extraction in hierarchical designs

Computer program product for timing analysis of integrated circuit

Phase algebra for specifying clocks and modes in hierarchical designs

Standard cell design with reduced cell delay

Static timing analysis in circuit design

Timing violation resilient asynchronous template

Method and design apparatus

Method of operating simulator compensating for delay and device for performing the same

System-on-chip verification

Integrated circuit device configuration methods adapted to account for retiming

Signal delay flip-flop cell for fixing hold time violation

Semiconductor having cross coupled structure and layout verification method thereof

System and method for efficient statistical timing analysis of cycle time independent tests

System and method for efficient statistical timing analysis of cycle time independent tests

Conditional phase algebra for clock analysis

Selectively reducing graph based analysis pessimism

Augmented simulation method for waveform propagation in delay calculation

Standard cell library and methods of using the same

Clock-tree transformation in high-speed ASIC implementation

Path-based floorplan analysis

Generating asserted sensitivities for statistical timing

System and method for maintaining slack continuity in incremental statistical timing analysis

Integrated circuit design synthesis using slack diagrams

Clock-gating phase algebra for clock analysis

Circuit design analyzer

Measurement of Aggressor/Victim capacitive coupling impact on timing

Margin tool for double data rate memory systems

Layout modification method and system

LSI DESIGN METHOD