189497 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices; Denomination or exception handling, e.g. rounding or overflow; Exception handling; Overflow or underflow Saturation, i.e. clipping the result to a minimum or maximum value
Neural network device, method of operating the neural network device, and application processor including the neural network device
#2Arithmetic circuitry for power-efficient multiply-add operations
#3Systems and methods for performing vector max/min instructions that also generate index values
#4SYSTEMS, APPARATUSES, AND METHODS FOR VECTOR-PACKED FRACTIONAL MULTIPLICATION OF SIGNED WORDS WITH ROUNDING, SATURATION, AND HIGH-RESULT SELECTION
#5Apparatus and method for performing conversion operation
#6Apparatus and method for performing conversion operation
#7Apparatus and method for vector processing
#8Vector operands with component representing different significance portions
#9Exception generation when generating a result value with programmable bit significance
#10Exponent monitoring
#11Significance alignment
#12Data processing apparatus and method using programmable significance data
#13Predicting saturation in a shift operation
#14Division circuit and microprocessor
#15Apparatuses and related methods for overflow detection and clamping with parallel operand processing
#16Packing odd bytes from two source registers of packed data
#17Orderly storing of corresponding packed bytes from first and second source registers in result register
#18Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements
#19Packing in destination register half of each element with saturation from two source packed data registers
#20Processor executing unpack and pack instructions specifying two source packed data operands and saturation
#21Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers
#22Interleaving half of packed data elements of size specified in instruction and stored in two source registers
#23Processor for performing multiply-add operations on packed data
#24Processor for performing multiply-add operations on packed data
#25Processor executing pack and unpack instructions
#26Method and apparatus for performing multiply-add operations on packed data
#27Packing two packed signed data in registers with saturation
#28Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation
#29Arithmetic logic unit for use within a flight control system
#30Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor
#31DSP engine with implicit mixed sign operands
#32Division unit, image analysis unit and display apparatus using the same
#33System and method for the parallelization of saturated accumulation operations
#34System and method to perform fast rotation operations
#35Packed add-subtract operation in a microprocessor
#36Processor for performing multiply-add operations on packed data
#37Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation
#38Methods and apparatus for implementing a saturating multiplier
#39Speed-level calculator and calculating method for dynamic voltage scaling
#40SATURATION AND ROUNDING IN MULTIPLY-ACCUMULATE BLOCKS
#41RECONFIGURABLE CIRCUIT
#42Multiplication Apparatus
#43DIVISION UNIT, IMAGE ANALYSIS UNIT AND DISPLAY APPARATUS USING THE SAME
#44Packed add-subtract operation in a microprocessor
#45Specialized processing block for programmable logic device
#46Method of operand width reduction to enable usage of narrower saturation adder
#47Pre-saturating fixed-point multiplier
#48Overflow detection and clamping with parallel operand processing for fixed-point multipliers
#49Simple and amended saturation for pipelined arithmetic processors
#50Method and system for pipelining saturated accumulation and other loops with loop-carried dependencies
#51Interleaving saturated lower half of data elements from two source registers of packed data
#52Method and system for dynamic session control of digital signal processing operations
#53Precision cordic processor
#54Method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations
#55Arithmetic unit
#56Method and system for saturating a left shift result using a standard shifter
#57Arithmetic unit
#58Processor having parallel vector multiply and reduce operations with sequential semantics
#59Method and system for performing parallel integer multiply accumulate operations on packed data
#60Saturating shift mechanisms within data processing systems
#61Saturation and rounding in multiply-accumulate blocks
#62Arithmetic unit for addition or subtraction with preliminary saturation detection
#63Method for performing single instruction multiple data operations on packed data
#64System and method for DMA transfer of data in scatter/gather mode
#65Method and system for performing parallel integer multiply accumulate operations on packed data