ClassID:

189511

G06F7/49994 - CPC Classification

Classification description:

Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices; Denomination or exception handling, e.g. rounding or overflow Sign extension

Recent Application in this class:
#1
20250156186
2025-05-15

Forming Constant Extensions in the Same Execute Packet in a VLIW Processor

#2
20230325189
2023-10-12

Forming constant extensions in the same execute packet in a VLIW processor

#3
20230196086
2023-06-22

Increased precision neural processing element

#4
20220326909
2022-10-13

TECHNIQUE FOR BIT UP-CONVERSION WITH SIGN EXTENSION

#5
20200410329
2020-12-31

Increased precision neural processing element

#6
20200310807
2020-10-01

Method for forming constant extensions in the same execute packet in a VLIW processor

#7
20200201600
2020-06-25

Multiple modes for handling overflow conditions resulting from arithmetic operations

#8
20170160944
2017-06-08

Integrating sign extensions for loads

#9
20170115989
2017-04-27

Method for forming constant extensions in the same execute packet in a VLIW processor

#10
20120215826
2012-08-23

System and method to implement a matrix multiply unit of a broadband processor

#11
20100306292
2010-12-02

DSP engine with implicit mixed sign operands

#12
20090198758
2009-08-06

METHOD FOR SIGN-EXTENSION IN A MULTI-PRECISION MULTIPLIER

#13
20090094309
2009-04-09

System and method to implement a matrix multiply unit of a broadband processor

#14
20080256165
2008-10-16

Full-Adder Modules and Multiplier Devices Using the Same

#15
20070239810
2007-10-11

Method and apparatus for providing packed shift operations in a processor

#16
20070192399
2007-08-16

Power-efficient sign extension for booth multiplication methods and systems

#17
20060235914
2006-10-19

Method and apparatus for providing packed shift operations in a processor

#18
20060143259
2006-06-29

Low power vector summation apparatus

#19
20060020653
2006-01-26

Method and system for digital signal processing, program product therefor

#20
20050235026
2005-10-20

Method and system for performing parallel integer multiply accumulate operations on packed data

#21
20050223054
2005-10-06

Multiplier sign extension method and architecture

#22
20050219897
2005-10-06

Method and apparatus for providing packed shift operations in a processor

#23
20050027969
2005-02-03

Method for performing single instruction multiple data operations on packed data

#24
20050027901
2005-02-03

System and method for DMA transfer of data in scatter/gather mode

#25
20050027773
2005-02-03

Method and system for performing parallel integer multiply accumulate operations on packed data

#26
15944315
2020-08-18

Core for a data processing engine in an integrated circuit

#27
14952078
2017-03-21

Integrating sign extensions for loads