189527 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices; Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
Sub-classes:CALCULATION DEVICE, CALCULATION PROGRAM, RECORDING MEDIUM, AND CALCULATION METHOD
#2MASKED SHIFTED ADD OPERATION
#3COMPUTING DEVICE, COMPUTING APPARATUS AND METHOD OF WARP ACCUMULATION
#4High-precision anchored-implicit processing
#5XIU-ACCUMULATING REGISTER, XIU-ACCUMULATING REGISTER CIRCUIT, AND ELECTRONIC DEVICE
#6Full adder cell with improved power efficiency
#7Full adder cell with improved power efficiency
#8Determining sums using logic circuits
#9Multiplier circuit
#10A CALCULATION DEVICE FOR ENCODED ADDITION
#11Integrated circuit design
#12Circuitry for low-precision deep learning
#13Continuous carry-chain packing
#14Circuit for addition of multiple binary numbers
#15Reduction operation mapping systems and methods
#16Adder device, data accumulation method and data processing device
#17Circuit for addition of multiple binary numbers
#18Comparator and memory region detection circuitry and methods
#19System and method for processing data in an adder based circuit
#20Reducing power consumption in a fused multiply-add (FMA) unit of a processor
#21HIGH-SPEED THREE-OPERAND N-BIT ADDER
#22Apparatus and method for performing absolute difference operation
#23Multi-element comparison and multi-element addition
#24Fused multiply-adder with booth-encoding
#25Method and apparatus for synthesising a sum of addends operation and an integrated circuit
#26Fused multiply-adder with booth-encoding
#27Reducing power consumption in a fused multiply-add (FMA) unit of a processor
#28Software-hardware adder
#29DSP BLOCK WITH EMBEDDED FLOATING POINT STRUCTURES
#30Look up table (LUT) structure supporting exclusive or (XOR) circuitry configured to allow for generation of a result using quaternary adders
#31Floating point collect and operate
#32Method of addition with multiple operands, corresponding adder and computer program product
#33System and method of using common adder circuitry for both a horizontal minimum instruction and a sum of absolute differences instruction
#34ARITHMETIC CIRCUIT AND POWER SAVING METHOD
#35Trigonometric summation vector execution unit
#36System and method for the parallelization of saturated accumulation operations
#37Adder, Synthesis Device Thereof, Synthesis Method, Synthesis Program, and Synthesis Program Storage Medium
#38Arithmetic or logical operation tree computation
#39Hash function implemention with ROM and CSA
#40Universal execution unit
#41SMART ACCUMULATOR FOR FINITE-PRECISION ARITHMETIC
#42Methods and apparatus for providing a reduction array
#43Method and a circuit using an associative calculator for calculating a sequence of non-associative operations
#44Processing method and computer system for summation of floating point data
#45Carry-ripple adder
#46System and method of performing two's complement operations in a digital signal processor
#47Hybrid arithmetic logic unit
#48Data value addition
#49Long-integer multiplier
#50Implementation of digital signal processing functions using maximal efficiency and minimal energy dissipation
#51SIMD processor having enhanced operand storage interconnects
#52Apparatus and method for converting, and adder circuit
#53Arithmetic circuit with multiplexed addend inputs
#54Multi-input floating-point adder