189520 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices; Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
Sub-classes:BIT-PARALLEL DIGITAL COMPUTE-IN-MEMORY MACRO AND ASSOCIATED METHOD
#2Device and Method of Handling a Modular Multiplication
#3OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS
#4Apparatus and method for performing a stable and short latency sorting operation
#5Methods of manufacturing semiconductor devices by etching active fins using etching masks and forming source/drain layers on the active fins
#6OBLIVIOUS CARRY RUNWAY REGISTERS FOR PERFORMING PIECEWISE ADDITIONS
#7Multiple accumulate busses in a systolic array
#8QUANTUM CIRCUIT OPTIMIZATION USING WINDOWED QUANTUM ARITHMETIC
#9Measurement based uncomputation for quantum circuit optimization
#10Surface code computations using Auto-CCZ quantum states
#11Oblivious carry runway registers for performing piecewise additions
#12Sum address memory decoded dual-read select register file
#13Multiple accumulate busses in a systolic array
#14ADDER CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME
#15Measurement based uncomputation for quantum circuit optimization
#16APPARATUS AND METHOD FOR VECTOR HORIZONTAL ADD OF SIGNED/UNSIGNED WORDS AND DOUBLEWORDS
#17Methods of manufacturing semiconductor devices by etching active fins using etching masks
#18Interlayer exchange coupled adder
#19Device and Method of Handling a Modular Multiplication
#20Apparatus and method for performing a stable and short latency sorting operation
#21Measurement based uncomputation for quantum circuit optimization
#22Binary parallel adder and multiplier
#23CONSTRUCTION METHOD of MSD PARALLEL ADDER BASED ON TERNARY LOGIC OPERATOR
#24Adder circuitry for very large integers
#25Multi-addend adder circuit for stochastic computing
#26Fast binary counters based on symmetric stacking and methods for same
#27Surface code computations using auto-CCZ quantum states
#28Quantum circuit optimization using windowed quantum arithmetic
#29Oblivious carry runway registers for performing piecewise additions
#30Methods of manufacturing semiconductor devices by etching active fins using etching masks
#31Binary parallel adder and multiplier
#32Massively parallel neural inference computing elements
#33PROCESSING APPARATUS AND METHOD OF PROCESSING ADD OPERATION THEREIN
#34Circuits and devices adding binary operands based on variable quantity
#35Adder-subtractor circuit and method of controlling adder-subtractor circuit
#36Massively parallel neural inference computing elements
#37Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks
#38Apparatus and method for vector horizontal add of signed/unsigned words and doublewords
#39Adder circuitry for very large integers
#40Prefix network-directed addition
#41Processing circuitry for encoded fields of related threads
#42Methods of manufacturing semiconductor devices by etching active fins using etching masks
#43Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks
#44Energy-efficient variable power adder and methods of use thereof
#45Methods of manufacturing finFET semiconductor devices
#46Overflow detection for sign-magnitude adders
#47Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks
#48Processor supporting arithmetic instructions with branch on overflow and methods
#49Accuracy configurable adders and methods
#50Reduced-level two's complement arithmetic unit
#51ADDER CIRCUIT AND XIU-ACCUMULATOR CIRCUIT USING THE SAME
#52Generating partial sums
#53Near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine
#54ARITHMETIC CIRCUIT AND POWER SAVING METHOD
#55LARGE INTEGER SUPPORT IN VECTOR OPERATIONS
#56Shared parallel adder tree for executing multiple different population count operations
#57N-digit subtraction unit, N-digit subtraction module, N-digit addition unit and N-digit addition module
#58Method and apparatus for zero prediction
#59Packed add-subtract operation in a microprocessor
#60N bit adder and the corresponding adding method
#61Device, system and method of reduced-power memory address generation
#62Packed add-subtract operation in a microprocessor
#63Method and apparatus of dsp resource allocation and use
#64Arithmetic unit of arbitrary precision, operation method for processing data of arbitrary precision and electronic equipment
#65Arithmetic circuit
#66Reconfigurable circuit with programmable split adder
#67Method and system for performing parallel integer multiply accumulate operations on packed data
#68Method for performing single instruction multiple data operations on packed data
#69System and method for DMA transfer of data in scatter/gather mode
#70Method and system for performing parallel integer multiply accumulate operations on packed data
#71Cross-layer reconfigurable static random access memory (SRAM) based compute-in-memory macro and method for edge intelligence
#72Multiple accumulate busses in a systolic array
#73Multiple busses interleaved in a systolic array
#74Processing-memory architectures performing atomic read-modify-write operations in deep learning systems
#75Memristor-based adders using memristors-as-drivers (MAD) gates
#76Memristor-based adders using memristors-as-drivers (MAD) gates
#77Parallel processing circuitry for encoded fields of related threads