189682 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Microcontrol or microprogram arrangements; Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements; Arrangements for next microinstruction selection Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
Chaos Testing Prioritization Via Smart Weights Inference
#2LIVE FIRMWARE UPDATE SWITCHOVER
#3Live firmware update switchover
#4APPARATUS AND METHOD FOR SECURE, EFFICIENT MICROCODE PATCHING
#5Apparatus and method for secure, efficient microcode patching
#6Accelerator controller for inserting template microcode instructions into a microcode buffer to accelerate matrix operations
#7Device and method for a frequency modulated signal
#8Scheduler for amp architecture with closed loop performance and thermal controller
#9Controlling apparatus for industrial products
#10Memory devices, systems, and methods for updating firmware with single memory device
#11Systems and methods of parallel and distributed processing of datasets for model approximation
#12INFORMATION PROCESSING SYSTEM AND RELAY DEVICE
#13Hardware processors and methods for extended microcode patching and reloading
#14Hint instruction for managing transactional aborts in transactional memory computing environments
#15Closed loop performance controller work interval instance propagation
#16Scheduler for amp architecture using a closed loop performance and thermal controller
#17Scheduler for AMP architecture with closed loop performance controller using static and dynamic thread grouping
#18Scheduling of work interval objects in an AMP architecture using a closed loop performance controller
#19Scheduler for amp architecture using a closed loop performance controller and deferred inter-processor interrupts
#20Scheduler for AMP architecture with closed loop performance controller
#21Scheduler for amp architecture using a closed loop performance and thermal controller
#22MULTI-NULLIFICATION
#23Apparatus and method for system physical address to memory module address translation
#24INSTRUCTION SET ARCHITECTURES FOR FINE-GRAINED HETEROGENEOUS PROCESSING
#25Debug support for block-based processor
#26Instruction block address register
#27Prefetching instruction blocks
#28Broadcast channel architectures for block-based processors
#29Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
#30Multi-nullification
#31Write nullification
#32Store nullification in the target field
#33Implicit program order
#34Register read/write ordering
#35Dynamic generation of null instructions
#36Generation and use of memory access instruction order encodings
#37Multimodal targets in a block-based processor
#38Dense read encoding for dataflow ISA
#39Distinct system registers for logical processors
#40Block-based processor core composition register
#41Initiating instruction block execution using a register access instruction
#42Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor
#43Hint instruction for managing transactional aborts in transactional memory computing environments
#44Hint instruction for managing transactional aborts in transactional memory computing environments
#45Hint instruction for managing transactional aborts in transactional memory computing environments
#46Hint instruction for managing transactional aborts in transactional memory computing environments
#47Propagation of microcode patches to multiple cores in multicore microprocessor
#48Apparatus and method for updating set of limited access model specific registers in a microprocessor
#49Data processor device supporting selectable exceptions and method thereof
#50APPARATUS AND METHOD FOR REAL-TIME MICROCODE PATCH
#51MICROCODE PATCH EXPANSION MECHANISM
#52APPARATUS AND METHOD FOR FAST MICROCODE PATCH FROM MEMORY
#53ON-CHIP MEMORY PROVIDING FOR MICROCODE PATCH OVERLAY AND CONSTANT UPDATE FUNCTIONS
#54APPARATUS AND METHOD FOR FAST ONE-TO-MANY MICROCODE PATCH
#55Wireless data communications using FIFO for synchronization memory
#56MICROCODE PATCHING SYSTEM AND METHOD
#57Integrated circuit with functional state configurable memory and method of configuring functional states of the integrated circuit memory
#58Wireless data communications using FIFO for synchronization memory
#59System on a chip integrated circuit, processing system and methods for use therewith
#60Method and structure for replacing faulty operating code contained in a ROM for a processor
#61Dynamic field patchable microarchitecture
#62Systems and methods of parallel and distributed processing of datasets for model approximation