SECURE PROCESSOR FOR DETECTING AND PREVENTING EXPLOITS OF SOFTWARE VULNERABILITY

Branch target buffer with shared target bits

Methods and apparatus to insert profiling instructions into a graphics processing unit kernel

LOGIC CIRCUIT AND METHOD FOR CHECKING AND UPDATING PROGRAM COUNTER VALUES IN PIPELINE ARCHITECTURE

ENFORCING DATA PLACEMENT REQUIREMENTS VIA ADDRESS BIT SWAPPING

Fetch stage handling of indirect jumps in a processor pipeline

Reverse engineering detection by counting consecutive incremental branch instructions in an instruction register of a processor

Methods and apparatus to insert profiling instructions into a graphics processing unit kernel

Fetch stage handling of indirect jumps in a processor pipeline

Signal handling between programs associated with different addressing modes

Verified Stack Trace Generation And Accelerated Stack-Based Analysis With Shadow Stacks

Methods and systems to track kernel calls using a disassembler

Processor including debug unit and debug system

Input/output data transformations when emulating non-traced code with a recorded execution of traced code

Methods and apparatus to insert profiling instructions into a graphics processing unit kernel

Call stack sampling

Method of enforcing control flow integrity in a monolithic binary using static analysis

Apparatus and method for controlling execution of instructions

Determining branch targets for guest branch instructions executed in native address space

Branch target buffer for emulation environments

Method and device for updating a program

Apparatus and method for an early page predictor for a memory paging subsystem

Additional Channel for Exchanging Useful Information

Register restoring branch instruction

Branch instruction

Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system

Predicting and storing a predicted target address in a plurality of selected locations

Predicting and storing a predicted target address in a plurality of selected locations

Concurrent prediction of branch addresses and update of register contents

Providing a predicted target address to multiple locations based on detecting an affiliated relationship

Concurrent prediction of branch addresses and update of register contents

Providing a predicted target address to multiple locations based on detecting an affiliated relationship

Methods and apparatus to insert profiling instructions into a graphics processing unit kernel

APPARATUS AND METHOD FOR MEMORY SHARING BETWEEN COMPUTERS

Power saving branch modes in hardware

Apparatus and method for controlling instruction execution behaviour

Data processing system and method for executing block call and block return instructions

Hybrid lookahead branch target cache

Pipelined processor with multi-issue microcode unit having local branch decoder

Technologies for indirect branch target security

Accelerated execution of execute instruction target

System and Method for Tracing Data Addresses

Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor

Techniques for predicting a target address of an indirect branch instruction

Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor

Device and processing architecture for resolving execution pipeline dependencies without requiring no operation instructions in the instruction memory

Verifying branch targets

Guest to native block address mappings and management of native code storage

Computer processor that implements pre-translation of virtual addresses with target registers

Computer processor that implements pre-translation of virtual addresses

Computer processor with register direct branches and employing an instruction preload structure

Computer processor with address register file

Guest instruction block with near branching and far branching sequence construction to native instruction block

Accelerated execution of execute instruction target

Systems and methods for managing return stacks in a multi-threaded data processing system

Execution flow protection in microcontrollers

System and method for page-conscious GPU instruction

Kick-started run-to-completion processing method that does not involve an instruction counter

Kick-started run-to-completion processor having no instruction counter

Processor supporting arithmetic instructions with branch on overflow and methods

Compressed indirect prediction caches

System and method of data processing

Processors operable to allow flexible instruction alignment

Method and apparatus for device testing using multiple processing paths

Persistent relocatable reset vector for processor

Executing subroutines in a multi-threaded processing system

Instruction address encoding and decoding based on program construct groups

Custom chaining stubs for instruction code translation

Memory controllers

Qualifying Software Branch-Target Hints with Hardware-Based Predictions

Methods and Apparatus to Extend Software Branch Target Hints

Hard object: constraining control flow and providing lightweight kernel crossings

Branch target computation in secure start-up using an integrity datum and an adjustment datum

Using the least significant bits of a called function's address to switch processor modes

Major branch instructions with transactional memory

Major branch instructions

Major branch instructions

Major branch instructions with transactional memory

High-performance cache system and method

High-word facility for extending the number of general purpose registers available to instructions

Program flow control for multiple divergent SIMD threads using a minimum resume counter

Processor operable to ensure code integrity

System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions

Control flow integrity

Return address optimisation for a dynamic code translator

RETURN ADDRESS OPTIMISATION FOR A DYNAMIC CODE TRANSLATOR

Table call instruction for frequently called functions

LOW-LATENCY BRANCH TARGET CACHE

Controlling the execution of adjacent instructions that are dependent upon a same data condition

Guest instruction block with near branching and far branching sequence construction to native instruction block

Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor

Guest to native block address mappings and management of native code storage

Data processing circuit with a plurality of instruction modes for processing time-stationary encoded instructions, and method of operating/scheduling such data circuit

Looking ahead bytecode stream to generate and update prediction information in branch target buffer for branching from the end of preceding bytecode handler to the beginning of current bytecode handler

Extract cache attribute facility and instruction therefore

Generating predicted branch target address from two entries storing portions of target address based on static/dynamic indicator of branch instruction type

No-delay microsequencer

INDIRECT BRANCH PREDICTION BASED ON BRANCH TARGET BUFFER HYSTERESIS

Packet processor configured for processing features directed by branch instruction with logical operator and two feature selector fields

Indirect Branch Hint

Method for TCAM lookup using a key in multi-threaded packet processors

Method for paramaterized application specific integrated circuit (ASIC)/field programmable gate array (FPGA) memory-based ternary content addressable memory (TCAM)

Method and apparatus for efficient memory bank utilization in multi-threaded packet processors

Control plane packet processing and latency control

Method for real-time synchronization of ARP record in RSMLT cluster

Method for Media Access Control address learning and learning rate suppression

Processors operable to allow flexible instruction alignment

High-word facility for extending the number of general purpose registers available to instructions

System and method to evaluate a data value as an instruction

Cache-based pipline control method and system with non-prediction branch processing using a track table containing program information from both paths of a branch instruction

Data processor with a load instruction that branches based on a control register value and a bit or bits read from memory

Processor, co-processor, information processing system, and method for controlling processor, co-processor, and information processing system

Extract cache attribute facility and instruction therefore

Branch target buffer for emulation environments

Program flow control

BRANCH PREDICTION MECHANISM FOR PREDICTING INDIRECT BRANCH TARGETS

Data processing system with branch target addressing using upper and lower bit permutation

Obfuscating program by scattering sequential instructions into memory regions such that jumps occur with steps of both signs in equal frequency

Microprocessor with Compact Instruction Set Architecture

Dynamic allocation of resources in a threaded, heterogeneous processor

RISC PROCESSOR DEVICE AND ITS INSTRUCTION ADDRESS CONVERSION LOOKING-UP METHOD

Method and apparatus for providing platform independent secure domain

Tracking effective addresses in an out-of-order processor

MICROCOMPUTER AND DIVIDING CIRCUIT

Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit

SEMI-ABSOLUTE BRANCH INSTRUCTIONS FOR EFFICIENT COMPUTERS

Jump instruction having a reference to a pointer for accessing a branch address table

INDIRECT BRANCH PROCESSING PROGRAM AND INDIRECT BRANCH PROCESSING METHOD

Microcomputer and its instruction execution method

Apparatus and method for updating set of limited access model specific registers in a microprocessor

Device and method for bypassing a first program code portion with a replacement program code portion

Microprocessor with Compact Instruction Set Architecture

Branch prediction technique using instruction for resetting result table pointer

Data prefetching using indirect addressing

BRANCH TARGET BUFFER ADDRESSING IN A DATA PROCESSOR

System and method for Controlling restarting of instruction fetching using speculative address computations

Processor and method for workaround trigger activated exceptions

Methods computer program products and systems for unifying program event recording for branches and stores in the same dataflow

Branch target address cache storing direct predictions

Concurrent processing element system, and method

Extract cache attribute facility and instruction therefore

Branch target buffer addressing in a data processor

Feedback mechanism for dynamic predication of indirect jumps

Target-frequency based indirect jump prediction for high-performance processors

Partitioning processor resources based on memory usage

Data Processing Apparatus and Method for Handling Procedure Call Instructions

Method and a system for accelerating procedure return sequences

Processor architecture for concurrently fetching data and instructions

Pre-tracing instructions for CGA coupled processor in inactive mode for execution upon switch to active mode and continuing pre-fetching cache miss instructions

DIGITAL SIGNAL PROCESSOR CONTROL ARCHITECTURE

Target branch prediction using a plurality of tables

Thread optimized multiprocessor architecture

Branch prediction table storing addresses with compressed high order bits

MICROCOMPUTER AND DIVIDING CIRCUIT

System and method for optimizing branch logic for handling hard to predict indirect branches

Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating system

Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information

Compact representation of instruction execution path history

Processing element having dual control stores to minimize branch latency

Method, system, and computer program product for path-correlated indirect address predictions

Central processing unit having branch instruction verification unit for secure program execution

Microcomputer and method of setting operation of microcomputer

Protected function calling

Method for performing jump and translation state change at the same time

Method and arrangements for pipeline processing of instructions

Data processing system to calculate indexes into a branch target address table based on a current operating mode

Hiding memory latency

Information processing apparatus

MICROCODE PATCHING SYSTEM AND METHOD

Circuit and method for patching for program ROM

Transferring data between registers in a RISC microprocessor architecture

Using breakpoints for debugging in a RISC microprocessor architecture

Floating point exception handling in a risc microprocessor architecture

Processing System having a Plurality of Processing Units with Program Counters and Related Method for Processing Instructions in the Processing System

Using trap routines in a RISC microprocessor architecture

Apparatus for generating return address predictions for implicit and explicit subroutine calls

Operation-processing device, method for constructing the same, and operation-processing system and method

Reducing the size of a data stream produced during instruction tracing

SYSTEM AND METHOD FOR PREDICTING TARGET ADDRESS OF BRANCH INSTRUCTION UTILIZING BRANCH TARGET BUFFER HAVING ENTRY INDEXED ACCORDING TO PROGRAM COUNTER VALUE OF PREVIOUS INSTRUCTION

Highly integrated multiprocessor system

Secure address handling in a processor

Detecting the boundaries of memory in a RISC microprocessor architecture

Availability of space in a RISC microprocessor architecture

Operation-processing device, method for constructing the same, and operation-processing system and method

Method and apparatus for image blending

System for target branch prediction using correlation of local target histories including update inhibition for inefficient entries

Processor and processing method for reusing arbitrary sections of program code

Information processing device, compressed program producing method, and information processing system

Thread optimized multiprocessor architecture

Data processor

Stack underflow debug with sticky base

Securised microprocessor with jump verification

Instruction prefetch apparatus and instruction prefetch method

VALIDATING BRANCH RESOLUTION TO AVOID MIS-STEERING INSTRUCTION FETCH

Selecting subroutine return mechanisms

Integrated circuit device

Branch encoding before instruction cache write

Method and apparatus for processing conditonal branch instructions

Conditional execution per lane

Method and apparatus for image blending

Patching device for a processor

Partitioning processor resources based on memory usage

System and method for hiding memory latency

Method and system for branch target prediction using path information

Microcomputer and dividing circuit

Dynamic endian switching

Branch prediction in a pipelined processor

Processors operable to allow flexible instruction alignment

Determining target addresses for instruction flow changing instructions in a data processing apparatus

Operation processing device, system and method having register-to-register addressing

Processor including branch prediction mechanism for far jump and far call instructions

Method for processing branch operations

Instruction memory

Computation engine with extract instructions to minimize memory access

Early execution of conditional branch instruction with pc operand at which point target is fetched