Signal processor and signal processing method

Methods and apparatus for thread-based scheduling in multicore neural networks

System and method for efficient multi-GPU rendering of geometry by subdividing geometry

Transaction-enabled methods for providing provable access to a distributed ledger with a tokenized instruction set

Transaction-enabled methods for providing provable access to a distributed ledger with a tokenized instruction set for a biological production process

Transaction-enabled methods for providing provable access to a distributed ledger with a tokenized instruction set for a semiconductor fabrication process

Maintaining sequentiality for media management of a memory sub-system

Method and apparatus of providing a function as a service (faas) deployment of an application

Non-cached loads and stores in a system having a multi-threaded, self-scheduling processor

Command-aware hardware architecture

METHOD, ACCELERATOR, AND ELECTRONIC DEVICE WITH TENSOR PROCESSING

Input and output interfaces for transmitting complex computing information between AI processors and computing components of a special function unit

Programming language trigger mechanisms for parallel asynchronous enumerations

Advanced processor architecture

Coalescing adjacent gather/scatter operations

Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries

Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization

Method for control-flow integrity protection, apparatus, device and storage medium

APPARATUS FOR OPTIMIZED MICROCODE INSTRUCTIONS FOR DYNAMIC PROGRAMMING BASED ON IDEMPOTENT SEMIRING OPERATIONS

System for certificating and synchronizing virtual world and physical world

Apparatus and method for provisioning virtualized multi-tile graphics processing hardware

Accelerator, method of operating the same, and electronic device including the same

Streaming engine with error detection, correction and restart

Memory system architecture for multi-threaded processors

Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor

Deferred command execution

DYNAMIC WORKFLOW SELECTION USING STRUCTURE AND CONTEXT FOR SCALABLE OPTIMIZATION

Arithmetic processing device and semiconductor device with improved instruction retry

Compiler program, compiling method, information processing device

Circuitry for floating-point power function

System and method for auto-recovery in lockstep processors

Merged branch target buffer entries

Parallel load of mapping containers for database system start and restart operations

Task graph generation for workload processing

MULTI-OBJECTIVE OPTIMIZATION METHOD AND SYSTEM FOR MASTER PRODUCTION PLAN OF CASTING PARALLEL WORKSHOPS

Command delay

Partitioned backing store implemented in a distributed database

Agent-based throttling of command executions

Operational code storage for an on-die microprocessor

Processor for executing a loop acceleration instruction to start and end a loop

Efficient mitigation of side-channel based attacks against speculative execution processing architectures

Thread commencement using a work descriptor packet in a self-scheduling processor

SYSTEMS AND METHODS FOR OPTIMIZED QUANTUM SEARCHING

MULTI-PROCESSOR SYSTEM AND METHOD UTILIZING DISCRETE COMPONENT PROCESSOR ELEMENTS

DEFINING AND ACCESSING DYNAMIC REGISTERS IN A PROCESSOR SYSTEM

Method and apparatus for vector sorting

PORTABLE DIAGNOSTIC TOOL FOR A DRIVE CONTROLLER OF A POWER-ACTUATED WORKSTATION

Scalar core integration

Method and apparatus for vector permutation

Adaptive load coalescing for spatially proximate load requests based on predicted load request coalescence based on handling of previous load requests

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Cognitive issue description and multi-level category recommendation

Highly efficient inexact computing storage device

Instruction scheduling patterns on decoupled systems

Data transmitting and receiving system including clock and data recovery device and operating method of the data transmitting and receiving system

Device and processor for implementing resource index replacement

Coarse-grain reconfigurable array processor with concurrent handling of multiple graphs on a single grid

Scalable hardware thread scheduler

Software managed memory hierarchy

Microprocessor with pipeline control for executing of instruction at a preset future time

Operand pool instruction reservation clustering in a scheduler circuit in a processor

Adjustment of load access size by a multi-threaded, self-scheduling processor to manage network congestion

Method and device for executing instructions to perform artificial intelligence

Deep neural network accelerator with independent datapaths for simultaneous processing of different classes of operations

Method for an internal command of a first processing core with memory sub-system that caching identifiers for access commands

Microprocessor having self-resetting register scoreboard

Apparatus and method for predicting source operand values and optimized processing of instructions

High-level synthesis multiprocessor system and the like

Method and system for tuning graphics processing unit (GPU) parameters of a GPU kernel

Iterative indirect command buffers

Concept for controlling access to a data memory

Deep object graph traversal

Deep object graph traversal

Pipelining for step input dataset and output dataset

Program Execution Assistance Apparatus and Program Execution Assistance Method

System, apparatus and method for dynamically adjusting platform power and performance based on task characteristics

Vector embedding models for relational tables with null or equivalent values

Cooperative work-stealing scheduler

Distributed terminals network management, systems, interfaces and workflows

Material handling method, equipment, storage medium and computer device

Systems and methods for dynamic server control based on estimated script complexity

Systems and methods for determining a dependency of instructions

Storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array

Systems and methods for configurable ordered transformation of database content

Decentralized network protected IoT query resolution

Stream-based composition and monitoring server system and method

System and method for controlling the order of instruction execution by a target device

Graphical user interface for creating data structures used for computing simulated surfaces for animation generation and other purpose

Method of computing simulated surfaces for animation generation and other purposes

ELECTRONIC DEVICE FOR PROVIDING TRANSACTION INFORMATION AND OPERATING METHOD THEREOF

Thread weave for cross-instruction set architecture procedure calls

Control system for process data and method for controlling process data

Instruction executing method and apparatus, electronic device, and computer-readable storage medium

Process address space identifier virtualization using hardware paging hint

METHOD FOR ACCELERATING THE EXECUTION OF A SINGLE-PATH PROGRAM BY THE PARALLEL EXECUTION OF CONDITIONALLY CONCURRENT SEQUENCES

Methods and systems for processing data in a programmable data processing pipeline that includes out-of-pipeline processing

System and method of obtaining multiple factor performance gain in processing system

Executing cross-core copy instructions in an accelerator to temporarily store an operand that cannot be accommodated by on-chip memory of a primary core into a secondary core

Intelligent thread dispatch and vectorization of atomic operations

Method and apparatus for escape reorder mode using a codebook index for neural network model compression

Electronic device for scheduling based on heterogeneous multi-processor and operating method thereof

Dynamic modification of instructions that do not modify the architectural state of a processor

SYSTEMS AND METHODS FOR OPTIMIZING NESTED LOOP INSTRUCTIONS IN PIPELINE PROCESSING STAGES WITHIN A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT

Maintaining blocks of a blockchain in a partitioned blockchain network

System and method for efficient multi-GPU rendering of geometry by subdividing geometry

Accelerator for dense and sparse matrix computations

Partitioning a blockchain network

Highly integrated scalable, flexible DSP megamodule architecture

SYSTEM AND METHOD FOR GENERATING DATA-FLOW ANALYSIS PIPELINES

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Partitioning a blockchain network

PARTITIONING A BLOCKCHAIN NETWORK

Partitioning a blockchain network

Flexible hardware for high throughput vector dequantization with dynamic vector length and codebook size

Method and apparatus for predicting and scheduling copy instruction for software pipelined loops

Predicated looping on multi-processors for single program multiple data (SPMD) programs

Method, system, and computer program product for dynamically assigning an inference request to a CPU or GPU

Memory IC with data loopback

Techniques for preventing concurrent execution of declarative infrastructure provisioners

Environment agnostic configuration with a declarative infrastructure provisioner

Meta-automated machine learning with improved multi-armed bandit algorithm for selecting and tuning a machine learning algorithm

Communicating an event to a remote entity

Performance monitoring for storage system with core thread comprising internal and external schedulers

Techniques for implementing rollback of infrastructure changes in a cloud infrastructure orchestration service

Techniques for deploying infrastructure resources with a declarative provisioning tool

Techniques for managing drift in a deployment orchestrator

Techniques for resolving application updates

Techniques for detecting drift in a deployment orchestrator

Techniques for utilizing directed acyclic graphs for deployment instructions

Techniques for managing long-running tasks with a declarative provisioner

Processing pipeline with first and second processing modes having different performance or energy consumption characteristics

User interface techniques for an infrastructure orchestration service

Reach matrix scheduler circuit for scheduling instructions to be executed in a processor

Method and device for simultaneously decoding data in parallel to improve quality of service

Processor circuit and data processing method

Executing mutually exclusive vector instructions according to a vector predicate instruction

Enterprise branding configuration provisioning

METHOD AND SYSTEM TO SUPPORT INDEXING IN ROW-GROUP COLUMNAR STORAGE

Systems and methods for optimizing nested loop instructions in pipeline processing stages within a machine perception and dense algorithm integrated circuit

Processing-in-memory (PIM) system and operating methods of the PIM system

System and method for the segmentation of a processor architecture platform solution

Function arbitration and quality of service for memory commands

Intelligent scheduling of coprocessor execution

Hardware apparatuses, methods, and systems for individually revocable capabilities for enforcing temporal memory safety

Neural network data processing apparatus, method and electronic device

MASTER TRANSFORM ARCHITECTURE FOR DEEP LEARNING

System and method for optimizing transmission of requests for updated content from external data sources

Maintaining sequentiality for media management of a memory sub-system

System and methods for tag-based synchronization of tasks for machine learning operations

Automatic working system, forwarding device, and task execution device

Methods and apparatus for continuous monitoring of telemetry in the field

Systems and methods for providing management of machine learning components

Systems and methods for situation awareness

Information sharing platform and method capable of providing bidirectional vehicle state information and system having information sharing platform

Tracking streaming engine vector predicates to control processor execution

Control system for artificial intelligence device and method thereof

Marker-based processor instruction grouping

Secure strong mapping computing systems, methods, secure computing apparatus and program

SYSTEM AND METHOD FOR PROVIDING A REPORT OF AN ANALYTIC RESULT VALUE BASED ON IP DATA

Managing the creation and execution of update campaigns in an multitenancy hierarchy

Redistributing update resources during update campaigns

High-level programming language which utilizes virtual memory

Pipelines for secure multithread execution

Hardware accelerator having reconfigurable instruction set and reconfigurable decoder

Systems and methods for controlling machine operations within a multi-dimensional memory space

Dynamic designation of instructions as sensitive for constraining multithreaded execution

Data structure descriptors for deep learning acceleration

Execution circuits using discardable state

Vehicle master device, rewrite target group administration method, computer program product and data structure of specification data

Memristor based storage of asset events

System for transforming legacy items contained in a data archive for execution or use by an executable

Drive control method and apparatus, and display device

Executing Memory Requests Out of Order

Automated concurrency and repetition with minimal syntax

Techniques for performing store-to-load forwarding

PROCESS FOR CONSTRUCTING A SIGNATURE CHARACTERISTIC OF THE ACCESSES, BY A MICROPROCESSOR, OF A MEMORY

Managing dispersed storage network background tasks

Vehicle master device, vehicle electronic control system, activation request instruction method and computer program product

Two address translations from a single table look-aside buffer read

Pre-instruction scheduling rematerialization for register pressure reduction

Center device, vehicle electronic control system, program update progress control method, and program update progress control program

INTELLIGENT IMAGE SENSOR STACK

System and method for enhancing the efficiency of mainframe operations

Storage medium, and method and system for simulating photography in virtual reality scene

Code and data sharing among multiple independent processors

Systems, methods, and apparatuses for dot production operations

Storage medium, control method, and management system

Scalable and dynamic data collection and processing

Priority-based CPU multitasking system and method

Storing a result of a first instruction of an execute packet in a holding register prior to completion of a second instruction of the execute packet

Storage devices mapped to registers and mapping methods thereof

Method, apparatus, and system for providing a broker for data modeling and code generation

Safe, secure, virtualized, domain specific hardware accelerator

Methods and apparatus to generate graphics processing unit long instruction traces

Multiported parity scoreboard circuit

Methods, systems and computer-readable mediums for position control of a machine

Protecting against out-of-bounds buffer references

Technology for dynamically tuning processor features

METHODS AND SYSTEMS FOR TIME-BOUNDING EXECUTION OF COMPUTING WORKFLOWS

Task processing method and apparatus, terminal, and computer readable storage medium

Scheduling tasks using targeted pipelines

Processing system with a main processor pipeline and a co-processor pipeline

Balancing high energy events

Query processing using data processing units having DFA/NFA hardware accelerators

Merge execution unit for microinstructions

Synchronous operation of peripheral devices

Systems and methods for generating a pipeline of stages for a process

Apparatus and method for store pairing with reduced hardware requirements

Method and apparatus for minimally intrusive instruction pointer-aware processing resource activity profiling

Incremental code generation method

Transpose operations using processing element array

SYSTEMS AND METHODS FOR CONTROLLED IP ACCESS USING A DISTRIBUTED LEDGER

Inter-thread communication in multi-threaded reconfigurable coarse-grain arrays

Controlling the operating speed of stages of an asynchronous pipeline

Instruction processing apparatuses, processors, and processing methods

DEEP LEARNING IMPLEMENTATIONS USING SYSTOLIC ARRAYS AND FUSED OPERATIONS

Tracking and communication of direct/indirect source dependencies of producer instructions executed in a processor to source dependent consumer instructions to facilitate processor optimizations

System, device, and method for obtaining instructions from a variable-length instruction set

Architecture to support synchronization between core and inference engine for machine learning

Information processing apparatus, non-transitory computer-readable storage medium for storing information processing program, and information processing method

Scheduling tasks using swap flags

Communication processor handling communications protocols on separate threads

Peridynamic method having additional mirroring node, and numerical analysis apparatus using same

Multi-thread wireless communications processor with granular thread processes

Multi-threaded processor with thread granularity

Hardware acceleration for function processing

Speculatively executing instructions that follow a status updating instruction

SYSTEM, MODIFICATION APPARATUS, METHOD, AND PROGRAM

Command delay

Selectively dispatching waves based on accumulators holding behavioral characteristics of waves currently executing

SYSTEM FOR STRUCTURING OBJECTS FOR OPERATION IN SOFTWARE ENVIRONMENTS AND METHODS FOR ITS IMPLEMENTATION

SYSTEMS AND METHODS FOR ARRANGING TRANSPORT OF ADAPTED NUTRIMENTAL ARTIFACTS WITH USER-DEFINED RESTRICTION REQUIREMENTS USING ARTIFICIAL INTELLIGENCE

Dataflow Triggered Tasks for Accelerated Deep Learning

Performance analysis system for analyzing processing performance of processing device and method thereof

Apparatus and method for operating an issue queue

SYSTEMS AND METHODS FOR POST CACHE INTERLOCKING

ARRAY-BASED INFERENCE ENGINE FOR MACHINE LEARNING

Method for processing event data flow and computing device

Reducing operations of sum-of-multiply-accumulate (SOMAC) instructions

Method and apparatus for counting foot step based on stride frequency, and device

Computer-implemented systems and methods for serialisation of arithmetic circuits

Policy handling for data pipelines

PROCESSING UNIT, PROCESSOR, PROCESSING SYSTEM, ELECTRONIC DEVICE AND PROCESSING METHOD

Parallel multiscale reservoir simulation

Parallel processing for malware detection

Information processing apparatus, method, and non-transitory computer-readable storage medium for storing control program of information processing apparatus

Latency-based instruction reservation station clustering in a scheduler circuit in a processor

Providing code sections for matrix of arithmetic logic units in a processor

Entanglement of pages and guest threads

Device such as a connected object provided with means for checking the execution of a program executed by the device

Target injection safe method for inlining registration calls

Managing commit order for an external instruction relative to queued instructions

Memory controller and memory system for generating instruction set based on non-interleaving block group information

Energy efficient processor core architecture for image processor

Apparatus and method for provisioning virtualized multi-tile graphics processing hardware

Apparatuses, methods, and systems for enhanced matrix multiplier architecture

CORE-TO-CORE "SNOOP" INSTRUCTION VARIANTS

Core-to-core end “offload” instruction(s)

Operand-based reach explicit dataflow processors, and related methods and computer-readable media

METHODS, DEVICES, AND MEDIA FOR PROCESSING LOOP INSTRUCTION SET

Transpose operations using processing element array

Operating system architecture for microkernel generations support

Instruction execution method and instruction execution device

SYSTEMS, METHODS, AND APPARATUS FOR UTILIZING FORWARD MARKET PRICING TO FACILITATE OPERATIONAL DECISIONS

Continuation analysis tasks for GPU task scheduling

METHODS FOR RESOURCE ALLOCATION AND UTILIZATION BASED ON FORWARD MARKET PRICE FORECAST

SYSTEMS, METHODS, AND APPARATUS FOR UTILIZING FORWARD MARKET PRICING TO FACILITATE OPERATIONAL DECISIONS

SYSTEMS, METHODS, AND APPARATUS FOR UTILIZING FORWARD MARKET PRICING TO FACILITATE OPERATIONAL DECISIONS

Multiprocessor utility meter featuring a metrology processor coupled to an application processor

Method and apparatus for vector based finite impulse response (FIR) filtering

Method and apparatus to sort a vector for a bitonic sorting algorithm

Method and apparatus for vector sorting using vector permutation logic

Instruction scheduling during execution in a processor

Processing device with vector transformation execution

Method and apparatus for permuting streamed data elements

Method and apparatus for vector based matrix multiplication

Method and apparatus for dual multiplication units in a data path

Method and apparatus for vector sorting

Method and apparatus for dual issue multiply instructions

Hybrid control module status communication system and method

Method and apparatus for implied bit handling in floating point multiplication

Power management

WAVELET REPRESENTATION FOR ACCELERATED DEEP LEARNING

Method, apparatus, and electronic device for improving parallel performance of CPU

System and method of VLIW instruction processing using reduced-width VLIW processor

Audio sample playback unit

Systemic extensible blockchain object model comprising a first-class object model and a distributed ledger technology

Method and system for instruction block to execution unit grouping

OPERATION FLOW GENERATION APPARATUS, SYSTEM, STORAGE MEDIUM AND OPERATION FLOW GENERATION METHOD

Engine to enable high speed context switching via on-die storage

Processing system for dispatching tasks and memory access method thereof

Processing system and heterogeneous processor acceleration method

Method, a device, and a computer program product for determining a resource required for executing a code segment

Information processing system, information processing device, and information processing method

METHOD AND APPARATUS FOR INTERRUPT DETECTION

SECURED DEPLOYMENT OF MACHINE LEARNING MODELS

Method for analysis on interim result data of de-identification procedure, apparatus for the same, computer program for the same, and recording medium storing computer program thereof

Performance profiling for a multithreaded processor

Apparatus and method for processing an image data stream by comparing first and second checking data streams

Scheduling tasks using work fullness counter