Asynchronous kernel

Signal processor and signal processing method

Instruction and logic for tracking fetch performance bottlenecks

Visual virtual programming machine for real-time interactive creation, playback, execution, inspection and manipulation of programming elements

Reporting and configuration enhancements of on-board certified software

Systems and methods for customization of workflow design

Reduction of data cache access in a processing system

Method for forming constant extensions in the same execute packet in a VLIW processor

Mitigating voltage droop

Method and apparatus for providing 360 stitching workflow and parameter

Graphics processing unit operation

Generative memory for lifelong machine learning

Convolutional layer acceleration unit, embedded system having the same, and method for operating the embedded system

Circuitry to indicate an execution mode to access a secondary device

Reach-based explicit dataflow processors, and related computer-readable media and methods

ELECTRONIC DEVICE AND METHOD FOR IMPLEMENTING PARTITIONING DURING THE EXECUTION OF SOFTWARE APPLICATIONS ON A PLATFORM COMPRISING A MULTI-CORE PROCESSOR, ASSOCIATED COMPUTER PROGRAM AND ELECTRONIC SYSTEM

Making precise operand-store-compare predictions to avoid false dependencies

Method and apparatus to efficiently process and execute Artificial Intelligence operations

Scalar core integration

Arithmetic processor and control method for arithmetic processor

METHOD AND DISTRIBUTED DATABASE SYSTEM FOR COMPUTER-AIDED EXECUTION OF A PROGRAM CODE

Pipeline including separate hardware data paths for different instruction types

SYSTEM AND METHOD FOR ADJUSTING FACILITY CONFIGURATION BASED ON MODEL SIMULATION ON A DIGITAL TWIN

SYSTEM AND METHOD FOR MACHINE FORWARD ENERGY PURCHASE BASED ON MODEL SIMULATION ON A DIGITAL TWIN

SYSTEMS AND METHODS FOR EXECUTING A CRYPTO-CURRENCY TRANSACTION IN RESPONSE TO A PREDICTED FORWARD MARKET PRICE

METHODS FOR ADJUSTING AN OPERATION OF A TASK SYSTEM OR EXECUTING A TRANSACTION IN RESPONSE TO A FORECAST OF A FORWARD MARKET VALUE

SYSTEM AND METHOD FOR PROVIDING A REPORT OF AN ANALYTIC RESULT VALUE BASED ON IP DATA

SYSTEM, METHODS, AND APPARATUS FOR ARBITRAGE ASSISTED RESOURCE TRANSACTIONS

SYSTEMS AND METHODS FOR UTILIZING SOCIAL MEDIA DATA TO AUTOMATICALLY EXECUTE A RESOURCE TRANSACTION

Method, apparatus, and electronic device for improving parallel performance of CPU

Providing, in a configuration packet, data indicative of data flows in a processor with a data flow manager

Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM

System and method for variable lane architecture

Streaming engine with error detection, correction and restart

Task optimization method and task optimization device in mobile robot

SYSTEM AND METHOD FOR ADAPTIVELY IMPROVING AN ENERGY DELIVERY

SYSTEM AND METHOD FOR ADJUSTING A FACILITY CONFIGURATION BASED ON A SET OF PARAMETERS FROM A DIGITAL TWIN

System and method for adjusting a facility configuration based on detected conditions

SYSTEM AND METHOD FOR ENABLING FIRMWARE TRANSACTIONS

SYSTEM AND METHOD FOR ENABLING A TRANSACTION

Task execution in a SIMD processing unit with parallel groups of processing lanes

Method and apparatus for the design and optimization of 3D frequency selective surfaces using evolutonary computing techniques

Adjusting thread balancing in response to disruptive complex instruction

Reduction of interrupt service latency in multi-processor systems

INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM

Apparatus and branch prediction circuitry having first and second branch prediction schemes, and method

Instruction interrupt suppression of overflow exception

SYSTEM AND METHOD FOR ADJUSTING A CONFIGURATION OF A FACILITY AI COMPONENT TO PRODUCE A FAVORABLE FACILITY OUTPUT VALUE

SYSTEM AND METHOD FOR PREDICTING A PRESENT STATE FACILITY OUTCOME VALUE BASED ON HISTORICAL FACILITY PARAMETER/OUTCOME VALUES

SYSTEM AND METHOD FOR COMMANDING AN EXECUTION OF A PLURALITY OF TRANSACTIONS IN RESPONSE TO AN IMPROVED AT LEAST ONE EXECUTION PARAMETER

SYSTEM AND METHOD FOR EXECUTING AN INCOMING TRANSACTION IN RESPONSE TO A TRANSACTION LOCATION PARAMETER ASSOCIATED WITH A PLURALITY OF TAX TREATMENT VALUES

Systems, methods, and apparatuses for tile load

Systems, methods, and apparatuses for tile broadcast

Speculatively releasing store data before store instruction completion in a processor

Information processing apparatus, non-transitory computer-readable medium, and information processing method

Resource management based on ranking of importance of applications

Completion mechanism for a microprocessor instruction completion table

Issuing instructions to multiple execution units

Systems, methods, and apparatus for tile configuration

Systems, methods, and apparatuses for zeroing a matrix

Enhancing processing performance of a DNN module by bandwidth control of fabric interface

Systems and methods for controlling machine operations using stack entries comprising instruction configuration parameters

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for matrix move

Computation engine with strided dot product

OPERATION CACHE

Method and system for detection of thread stall

Convolution operator system to perform concurrent convolution operations

Electronic control unit and method for verifying control program

Safe, secure, virtualized, domain specific hardware accelerator

Mask generation using reduction operators and scatter use thereof

Techniques for scheduling instructions in compiling source code

HARDWARE PROFILER TO TRACK INSTRUCTION SEQUENCE INFORMATION INCLUDING A BLACKLISTING MECHANISM AND A WHITELISTING MECHANISM

Arbitration techniques for managed memory

Methods and systems for verifying out-of-order page fault detection

Scheduling tasks in a processor

Handling exceptions in a multi-tile processing arrangement

Intelligent scheduling of coprocessor execution

Method and apparatus for supporting speculative memory optimizations

Method and apparatus to re-configure MDIO registers on an ethernet device

Change control management of continuous integration and continuous delivery

Memristor based storage of asset events

Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency

Apparatus and method of dispatching instructions for execution clusters based on dependencies

Validation of execution plan for configuring an information technology infrastructure

Apparatus and method for widened SIMD execution within a constrained register file

Method and system for protecting an aircraft against an incoherent command instruction

Handling effective address synonyms in a load-store unit that operates without address translation

Arithmetic processing apparatus and method for selecting an executable instruction based on priority information written in response to priority flag comparison

Management of the untranslated to translated code steering logic in a dynamic binary translation based processor

Determining branch targets for guest branch instructions executed in native address space

Information processing system and method for controlling information processing system

Flush-recovery bandwidth in a processor

Load balancing of machine learning algorithms

Data processing apparatus and method

Processing device and method of controlling processing device

METHODS AND APPARATUS TO OFFLOAD AND ONLOAD WORKLOADS IN AN EDGE ENVIRONMENT

Executing a composite scalar-vector VLIW instruction having a repeat field

Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines

Method and apparatus for data-ready memory operations

Method of logging process data in a PLC controlled equipment

Methods and apparatus to aggregate telemetry data in an edge environment

Multi-tenant data protection in edge computing environments

Task synchronization for accelerated deep learning

Semiconductor device

Methods, systems, articles of manufacture, and apparatus to optimize thread scheduling

Managing commit order for an external instruction relative to two unissued queued instructions

Universal pointers for data exchange in a computer system having independent processors

Adaptive dataflow transformation in edge computing environments

Dynamic sharing in secure memory environments using edge service sidecars

Decentralized edge computing transactions with fine-grained time coordination

TRANSACTION-ENABLED SYSTEMS AND METHODS FOR IDENTIFYING AND ACQUIRING MACHINE RESOURCES ON A FORWARD RESOURCE MARKET

Cache control circuitry and methods

Performance scaling for binary translation

SYSTEMS AND METHODS FOR FORWARD MARKET ENERGY PRICE PREDICTION AND MACHINE FORWARD ENERGY PURCHASE

TRANSACTION-ENABLED SYSTEMS AND METHODS WITH LICENSING SMART WRAPPERS AND IP LICENSING CHAINS

TRANSACTION-ENABLED SYSTEMS AND METHODS FOR APPORTIONING ROYALTY WITH IP LICENSING

SYSTEMS AND METHODS FOR AGGREGATING TRANSACTIONS AND OPTIMIZATION DATA RELATED TO ENERGY CREDITS

SYSTEMS AND METHODS FOR ALLOCATION OF RENEWABLE ENERGY CAPACITY FOR A FLEET OF MACHINES

Transaction-enabled systems and methods for transaction execution with licensing smart wrappers

Proactive voltage droop reduction and/or mitigation in a processor core

System and method for business process monitoring

SYSTEMS AND METHODS FOR FORWARD MARKET PURCHASE OF MACHINE RESOURCES USING ARTIFICIAL INTELLIGENCE

Transaction-enabled systems to forecast a forward market value and adjust an operation of a task system in response

Forward market renewable energy credit prediction from automated agent behavioral data

Forward market renewable energy credit prediction from human behavioral data

Transaction-enabled systems and methods for predicting a forward market price utilizing external data sources and resource utilization requirements

Transaction-enabled systems and methods to utilize a transaction location in implementing a transaction request

Data processing apparatus and method

Stream-based composition and monitoring server system and method

Data processing apparatus and method

Systems and methods for improving resource utilization for a fleet of machines

Data processing apparatus and method

Memory system architecture for multi-threaded processors

Providing predictive instruction dispatch throttling to prevent resource overflows in out-of-order processor (OOP)-based devices

Transaction-enabled systems and methods for identifying and acquiring machine resources on a forward resource market

Transaction-enabled systems and methods for providing provable access to a distributed ledger with serverless code logic

Micro-architecture designs and methods for eager execution and fetching of instructions

Systems and methods for aggregating transactions and optimization data related to energy and energy credits

TRANSACTION-ENABLED SYSTEMS AND METHODS WITH LICENSING SMART WRAPPERS AND IP AGGREGATION

SYSTEMS AND METHODS FOR FORWARD MARKET PRICE PREDICTION AND SALE OF ENERGY STORAGE CAPACITY WITH ARBITRAGE

SYSTEMS AND METHODS FOR MACHINE FORWARD ENERGY AND ENERGY STORAGE TRANSACTIONS

Systems and methods for machine forward energy transactions optimization

Systems and methods for machine forward energy and energy storage transactions

Systems and methods for fleet forward energy and energy credits purchase

SYSTEMS AND METHODS FOR ALLOCATION OF RENEWABLE ENERGY CAPACITY

Systems and methods for machine forward energy and energy credit purchase

SYSTEMS AND METHODS FOR FORWARD MARKET PURCHASE OF ATTENTION RESOURCES

Systems and methods for forward market purchase of machine resources

SYSTEMS AND METHODS FOR FLEET ENERGY ACQUISITION ON A SPOT MARKET

SYSTEMS AND METHODS FOR FLEET ENERGY ACQUISITION ON A SPOT MARKET

Systems and methods for forward market price prediction and sale of energy storage capacity

Systems and methods for arbitrage based machine resource acquisition

Transaction-enabled systems and methods for royalty apportionment and stacking

Energy management in graphics processing units

Processing of process data

Systems and methods for forward market price prediction and sale of energy credits

Transaction-enabled systems and methods for smart contracts

Dynamic fragmented address space layout randomization

Microprocessor including an efficiency logic unit

Hardware acceleration method, compiler, and device

Parallel processing for malware detection

Convergence among concurrently executing threads

System and method for scheduling a plurality of guest systems and/or threads

Independent mapping of threads

Systems, methods, and apparatuses for matrix operations

System and method for analyzing power usage of an energy-aware computing system

Highly efficient inexact computing storage device

Mechanism to stop completions using stop codes in an instruction completion table

Mechanism for completing atomic instructions in a microprocessor

Completion mechanism for a microprocessor instruction completion table

Arithmetic logic unit layout for a processor

System and method for populating multiple instruction words

SYSTEM AND METHOD FOR LOCATION AWARE PROCESSING

System and method of populating an instruction word

System and method for creating and executing an instruction word for simultaneous execution of instruction operations

System and method for low latency node local scheduling in distributed resource management

Computing Method Applied to Artificial Intelligence Chip, and Artificial Intelligence Chip

Apparatus and methods for matrix multiplication

Method and apparatus for executing instructions including a blocking instruction generated in response to determining that there is data dependence between instructions

STORAGE SYSTEM AND MANAGEMENT METHOD THEREOF

ANALYSIS NODE, METHOD FOR MANAGING RESOURCES, AND PROGRAM RECORDING MEDIUM

Parallel dispatching of multi-operation instructions in a multi-slice computer processor

Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor

Processor with a full instruction set decoder and a partial instruction set decoder

Low-cost task specific device scheduling system

Instruction completion table containing entries that share instruction tags

Processor trace extensions to facilitate real-time security monitoring

METHOD, APPARATUS AND DEVICE FOR UPDATING DATA, AND MEDIUM

Intelligent thread dispatch and vectorization of atomic operations

Clock-forwarding memory controller with mesochronously-clocked signaling interface

Cooperative workgroup scheduling and context prefetching based on predicted modification of signal values

INFORMATION PROCESSING DEVICE AND NON-TRANSITORY COMPUTER READABLE MEDIUM

Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator

Arithmetic processing apparatus and control method using ordering property

Decoupling of conditional branches

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

Method for detecting and recovery from soft errors in a computing device

Scheduling in a data processing apparatus

EXECUTION OF INSTRUCTIONS BASED ON PROCESSOR AND DATA AVAILABILITY

DYNAMIC ADJUSTMENT OF ISSUE-TO-ISSUE DELAY BETWEEN DEPENDENT INSTRUCTIONS

Hybrid decoding

Managing efficient selection of a particular processor thread for handling an interrupt

Scheduler queue assignment

Apparatus and method for storing source operands for operations

Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor

Transaction-enabled systems and methods for resource acquisition for a fleet of machines

Transaction-enabled methods for providing provable access to a distributed ledger with a tokenized instruction set

Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedback

Systems, methods, and apparatuses for matrix add, subtract, and multiply

Transaction-enabled systems for providing provable access to a distributed ledger with a tokenized instruction set

Systems, methods, and apparatuses for tile transpose

Transaction-enabled systems and methods for creating an aggregate stack of intellectual property

Systems and methods for enabling machine resource transactions for a fleet of machines

Transaction-enabling systems and methods for customer notification regarding facility provisioning and allocation of resources

Systems and methods for enabling machine resource transactions

Facility level transaction-enabling systems and methods for provisioning and resource allocation

Error detection using vector processing circuitry

Adjustment of load access size by a multi-threaded, self-scheduling processor to manage network congestion

Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor

Memory request size management in a multi-threaded, self-scheduling processor

Thread state monitoring in a system having a multi-threaded, self-scheduling processor

Non-cached loads and stores in a system having a multi-threaded, self-scheduling processor

Thread commencement and completion using work descriptor packets in a system having a self-scheduling processor and a hybrid threading fabric

Issuing and flushing instructions from reservation stations using wrap bits and indexes

Thread commencement using a work descriptor packet in a self-scheduling processor

Systems, methods, and apparatuses for tile diagonal

Preemptive scheduling of in-enclave threads

Run-time or compile-time error solutions for locating missing program elements in a programming environment

Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses

EXECUTING INSTRUCTIONS BASED ON A SHARED PHYSICAL REGISTER

Computation engine with strided dot product

Computation engine with upsize/interleave and downsize/deinterleave options

Decoupled processor instruction window and operand buffer

Executing load-store operations without address translation hardware per load-store unit port

INSTRUCTION SET ARCHITECTURE TO FACILITATE ENERGY-EFFICIENT COMPUTING FOR EXASCALE ARCHITECTURES

Parallel processing for malware detection

OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DATAPATH STEERING

Data processing systems

Control of redundant processing units

Vector processor, operation performing method, and non-transitory computer-readable recording medium for recording program

System and method to dynamically and automatically sharing resources of coprocessor AI accelerators

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Data structure descriptors for deep learning acceleration

Wavelet representation for accelerated deep learning

Scheduling of tasks in a multiprocessor device

Method for operating a processing unit

Processor checking method, checking device and checking system

Coalescing adjacent gather/scatter operations

Task execution in a SIMD processing unit with parallel groups of processing lanes

Systems and methods for programmable hardware architecture for machine learning

Architecture for dense operations in machine learning inference engine

Architecture of crossbar of inference engine

Streaming engine for machine learning architecture

Architecture for irregular operations in machine learning inference engine

Array-based inference engine for machine learning

Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine

Issuing instructions based on resource conflict constraints in microprocessor

Load/store unit for a processor, and applications thereof

Energy efficient processor core architecture for image processor

Multifunctional hexadecimal instruction form system and program product

Determining whether a flow is to be added to a network

Operation of a multi-slice processor implementing a hardware level transfer of an execution thread

DATA CONTROLLING METHOD OF DISTRIBUTED COMPUTING SYSTEM AND DISTRIBUTED COMPUTING SYSTEM

Processor device collecting performance information through command-set-based replay

Techniques for hybrid computer thread creation and management

Accessing data in multi-dimensional tensors

Apparatus and method for a hybrid latency-throughput processor

System and method for executing scripts in a virtual network function

Method and system for detection of thread stall

Data-less history buffer with banked restore ports in a register mapper

Differential pipeline delays in a coprocessor

Dynamic Workflow Control Based on Database Logic

Optimized multi-processor instruction scheduler

Performance scaling for binary translation

MANAGEMENT OF THE UNTRANSLATED TO TRANSLATED CODE STEERING LOGIC IN A DYNAMIC BINARY TRANSLATION BASED PROCESSOR

Head and tail pointer manipulation in a first-in-first-out issue queue

Executing processor instructions using minimal dependency queue

System and method for processing a load micro-operation by allocating an address generation scheduler queue entry without allocating a load queue entry

Mechanism for saving and retrieving micro-architecture context

Compiler for a processor comprising primary and non-primary functional units

Compiler for a processor comprising primary and non-primary functional units

Binding constants at runtime for improved resource utilization

Uniform register file for improved resource utilization

System and method of execution map generation for schedule optimization of machine learning flows

High performance processor system and method based on general purpose units

System and method of VLIW instruction processing using reduced-width VLIW processor

Managing efficient selection of a particular processor thread for handling an interrupt

Streaming engine with error detection, correction and restart

Spin loop delay instruction

Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses

Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor

Executing load-store operations without address translation hardware per load-store unit port

Handling effective address synonyms in a load-store unit that operates without address translation

Executing load-store operations without address translation hardware per load-store unit port

Handling effective address synonyms in a load-store unit that operates without address translation

Technologies for untrusted code execution with processor sandbox support