PROCESSING APPARATUS

Device and method for processing instructions based on masked register group size information

Instruction issue control within a multi-threaded in-order superscalar processor

Instructions for ordering execution in pipelined processes

Reconfigurable Computing Architectures: Dynamic and Steering Vector Methods

Microprocessor output ports and control of instructions provided therefrom

Thread scheduling on multiprocessor systems

Processing long-latency instructions in a pipelined processor

Method and system for autonomic monitoring of semaphore operations in an application

Circuit marginality validation test for an integrated circuit

System and method for executing instructions prior to an execution stage in a processor

Information processing apparatus

RELIABILITY MORPH FOR A DUAL-CORE TRANSACTION-PROCESSING SYSTEM

COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION REORDER BUFFER

Configurable Microprocessor

System and method for predictive early allocation of stores in a microprocessor

DATA PROCESSING SYSTEM

Method and apparatus for efficient resource utilization for prescient instruction prefetch

Computer with high-speed context switching

Method for latest producer tracking in an out-of-order processor, and applications thereof

STRUCTURE FOR REGISTER RENAMING IN A MICROPROCESSOR

Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations

Method and apparatus for back to back issue of dependent instructions in an out of order issue queue

Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch

Processor and its instruction issue method

Microprocessor including register renaming unit for renaming target registers in an instruction with physical registers in a register sub-file

Instruction controller to distribute serial and SIMD instructions to serial and SIMD processors

Control of metastability in the pipelined data processing apparatus

Method and apparatus for measuring pipeline stalls in a microprocessor

Hardware device for processing the tasks of an algorithm in parallel

Distributed dispatch with concurrent, out-of-order dispatch

Employing a buffer to facilitate instruction execution

Speculative instruction issue in a simultaneously multithreaded processor

Result data forwarding in parallel vector data processor based on scalar operation issue order

Method and apparatus for power throttling a processor in an information handling system

Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor

DESIGN STRUCTURE FOR DOUBLE-WIDTH INSTRUCTION QUEUE FOR INSTRUCTION EXECUTION

Register map unit supporting mapping of multiple register specifier classes

Computer processing system employing an instruction reorder buffer

Computer processing system employing an instruction schedule cache

Parallel Data Processing Apparatus

PARALLEL DATA PROCESSING APPARATUS

Method and apparatus to estimate energy consumed by central processing unit core

Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renaming

High Frequency Stall Design

Cascaded Delayed Execution Pipeline

System and method for implementing simplified arithmetic logic unit processing of value-based control dependence sequences

Apparatus with variable pipeline stages via unification processing and cancellation

Hierarchical register file with operand capture ports

Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions

Dynamic recalculation of resource vector at issue queue for steering of dependent instructions

Hierarchical instruction scheduler facilitating instruction replay

Hierarchical multi-threading processor for executing virtual threads in a time-multiplexed fashion

Hierarchical store buffer having segmented partitions

Data processing device with instruction controlled clock speed

Method and apparatus for segmented sequential storage

Method for latest producer tracking in an out-of-order processor, and applications thereof

Instruction Cache Trace Formation

Execution of instructions within a data processing apparatus having a plurality of processing units

Systems and methods for reconfiguring on-chip multiprocessors

Credit-based activity regulation within a microprocessor based on an accumulative credit system

System and method of power management for computer processor systems

Method And Apparatus For Improving The Efficiency Of A Processor Instruction Pipeline

Thread manager to control an array of processing elements

Vector processor and system for vector processing

Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion

Load/store unit for a processor, and applications thereof

Method for renaming a large number of registers in a data processing system using a background channel

Providing temporary storage for contents of configuration registers

Tracking multiple dependent instructions with instruction queue pointer mapping table linked to a multiple wakeup table by a pointer

Method and apparatus for timing and event processing in wireless systems

Restoring a register renaming table within a processor following an exception

Method and apparatus for timing and event processing in wireless systems

Overlapping command at one stage submitting method of dynamic cycle pipeline

Technique to clear bogus instructions from a processor pipeline

System for managing data dependency using bit field instruction destination vector identifying destination for execution results

Demand-based processing resource allocation

Processor system for varying clock frequency and voltage in response to a comparison of instruction execution rate to a reference value

System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue

Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor

Multi-sequence control for a data parallel system

Scheduling operations corresponding to store instructions

System and method of execution of register pointer instructions ahead of instruction issues

Memory access consolidation for SIMD processing elements using transaction identifiers

Method and apparatus for executing processor instructions based on a dynamically alterable delay

Processor device for out-of-order processing having reservation stations utilizing multiplexed arithmetic pipelines

Parallel data processing apparatus

Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions

Efficient interrupt return address save mechanism

Transitive suppression of instruction replay

Parallel data processing apparatus

Processor architecture for multipass processing of instructions downstream of a stalled instruction

START TRANSACTIONAL EXECUTION (STE) INSTRUCTION TO SUPPORT TRANSACTIONAL PROGRAM EXECUTION

Systems and methods for processing buffer data retirement conditions

System, method and medium processing data according to merged multi-threading and out-of-order scheme

PARALLEL DATA PROCESSING APPARATUS

PARALLEL DATA PROCESSING APPARATUS

PARALLEL DATA PROCESSING APPARATUS

Managing wasted active power in processors based on loop iterations and number of instructions executed since last loop

PARALLEL DATA PROCESSING APPARATUS

Prediction based instruction steering to wide or narrow integer cluster and narrow address generation

Double-Width Instruction Queue for Instruction Execution

System and method for simulating hardware interrupts

Simple load and store disambiguation and scheduling at predecode

Multi-threaded processor with deferred thread output control

Selectively monitoring loads to support transactional program execution

Sliding-window, block-based branch target address cache

Vector length tracking mechanism

SYSTEM AND METHOD FOR DYNAMICALLY ADJUSTING PIPELINED DATA PATHS FOR IMPROVED POWER MANAGEMENT

Selectively monitoring stores to support transactional program execution

BLOCK-BASED BRANCH TARGET ADDRESS CACHE

Method and system having instructions with different execution times in different modes, including a selected execution time different from default execution times in a first mode and a random execution time in a second mode

Methods and apparatus to detect data dependencies in an instruction pipeline

Vector processor

Method and apparatus for back to back issue of dependent instructions in an out of order issue queue

Parallel data processing apparatus

Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

PARALLEL DATA PROCESSING APPARATUS

Apparatus For Cooperative Sharing Of Operand Access Port Of A Banked Register File

High-performance RISC-DSP

Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors

Methods and apparatus to monitor instruction types and control power consumption within a processor

Multithreaded dynamic voltage-frequency scaling microprocessor

Method to detect a stalled instruction stream and serialize micro-operation execution

Processor apparatus for executing instructions with local slack prediction of instructions and processing method therefor

Working register file entries with instruction based lifetime

Patchable and/or programmable decode using predecode selection

Systems and methods for managing power consumption in data processors using execution mode selection

Instruction subgraph identification for a configurable accelerator

Compact linked-list-based multi-threaded instruction graduation buffer

Method for data validity tracking to determine fast or slow mode processing at a reservation station

Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture

Orderly processing ready entries from non-sequentially stored entries using arrival order matrix reordered upon removal of processed entries

System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor

Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number

Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready

Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system

Processor, multiprocessor system, processor system, information processing apparatus, and temperature control method

Device, system and method of handling FXCH instructions

Programmable processing unit providing concurrent datapath operation of multiple instructions

Configurable co-processor interface

Supporting out-of-order issue in an execute-ahead processor

Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss

Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis

Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines

Resource sharing in multiple parallel pipelines

Run-time selection of feed-back connections in a multiple-instruction word processor

Register allocation method and system for program compiling

Control of priority and instruction rates on a multithreaded processor

System and method for acceleration of streams of dependent instructions within a microprocessor

Dynamically self-decaying device architecture

Method and apparatus for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit

Loop accelerator and data processing system having the same

Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions

Method and apparatus for microarchitecture partitioning of execution clusters

PROCESSOR AND PIPELINE RECONFIGURATION CONTROL METHOD

Efficient counting for iterative instructions

Method for estimating processor energy usage

Decoupling register bypassing from pipeline depth

Stack tracker

Prefetch command control method, prefetch command control apparatus and cache memory control apparatus

Technique for setting a vector mask

Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip

Multithreading instruction scheduler employing thread group priorities

System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

High-performance, superscalar-based computer system with out-of-order instruction execution

Data processing apparatus

Processor core and method for managing branch misprediction in an out-of-order processor pipeline

System and method for handling load and/or store operations in a superscalar microprocessor

High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution

Flexible ordered execution mechanism for multi-threaded processors

Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor

APPARATUS AND METHOD TO TRACE HIGH PERFORMANCE MULTI-ISSUE PROCESSORS

Method and apparatus for delaying a load miss flush until issuing the dependent instruction

Multithread processor

Audio application programming interface

Time-of-life counter design for handling instruction flushes from a queue

Instruction packer for digital signal processor

Hierarchical processor

Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor

Data processing apparatus and data processing method for performing pipeline processing based on RISC architecture

Method and apparatus for issuing instructions from an issue queue in an information handling system

Program-controlled unit and method

Support for conditional operations in time-stationary processors

Power consumption management

Partially decoded register renamer

Preventing loss of traced information in a data processing apparatus

Power reduction for processor front-end by caching decoded instructions

Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power

Wakeup mechanisms for schedulers

System and method for high frequency stall design

Performance of a data processing apparatus

Data processing

System and method to manage data processing stages of a logical graphics pipeline

Instruction queues in pipelined processors

Pipeline processor, and method for automatically designing a pipeline processor

Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines

Method and system for an enhanced microprocessor

Microprocessor

Thread instruction issue pool counter decremented upon execution and incremented at desired issue rate

Emulator and emulating method for adjusting the execution timing of instructions included in an application to be emulated

System, apparatus and method of executing a micro operation

Register allocation technique

Method of renaming registers in register file and microprocessor thereof

Apparatus and method for switchable conditional execution in a VLIW processor

Real-time processor

Microprocessor with automatic selection of processing parallelism mode based on width data of instructions

Parallel processing system

A system and method for simulation of electronic circuits generating clocks and delaying the execution of instructions in a plurality of processors

Method and apparatus for instruction latency tolerant execution in an out-of-order pipeline

Apparatus and method for performing efficient multiply-accumulate operations in microprocessors

Selectively deferring instructions issued in program order utilizing a checkpoint and instruction deferral scheme

Result bypassing to override a data hazard within a superscalar processor

Dynamic fetch rate control of an instruction prefetch unit coupled to a pipelined memory system

Long instruction word processing with instruction extensions

Multiprocessor system for decrypting and resuming execution of an executing program after transferring the program code between two processors via a shared main memory upon occurrence of predetermined condition

Controlling out of order execution pipelines using pipeline skew parameters

Controlling out of order execution pipelines issue tagging

Configurable co-processor interface

Vector processor with special purpose registers and high speed memory access

Data access prediction

Processor and method for executing data transfer process

Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction

Command ordering among commands in multiple queues using hold-off vector generated from in-use vector and queue dependency scorecard

Processor and processor instruction buffer operating method

Selective power-down for high performance CPU/system

Credit-based activity regulation within a microprocessor based on an allowable activity level

System for predictive processor component suspension and method thereof

System and method for handling multi-cycle non-pipelined instruction sequencing

Mixed superscalar and VLIW instruction issuing and processing method and system

Command time-out managing apparatus

Performance of a data processing apparatus

Processor utilizing novel architectural ordering scheme

Reconfigurable processor array exploiting ilp and tlp

Methods and apparatus for improving processing performance using instruction dependency check depth

Method and apparatus for power reduction utilizing heterogeneously-multi-pipelined processor

HIGH-LEVEL LANGUAGE PROCESSOR APPARATUS AND METHOD

Selectively unmarking load-marked cache lines during transactional program execution

Multifunction hexadecimal instruction form

System and method of correcting a branch misprediction

Resolving all previous potentially excepting architectural operations before issuing store architectural operation

Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check

Programmable delayed dispatch in a multi-threaded pipeline

Method, apparatus and program product for enhancing performance of an in-order processor with long stalls

Localized generation of global flush requests while guaranteeing forward progress of a processor

Dynamic recalculation of resource vector at issue queue for steering of dependent instructions

Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch

Multithreading instruction scheduler employing thread group priorities

Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor

Processing apparatus including dedicated issue slot for loading immediate value, and processing method therefor

Method and apparatus for processing conditonal branch instructions

Processor including a register file and method for computing flush masks in a multi-threaded processing system

Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor

Two dimensional data access in a processor

Extended register bank allocation based on status mask bits set by allocation instruction for respective code block

Methods and systems for ordering instructions using future values

System and method for simulating hardware interrupts

Method and apparatus for vector execution on a scalar machine

Processor with automatic scheduling of operations

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Method and system for generating object code to facilitate predictive memory retrieval

Information processing apparatus and information processing method for autonomously controlling the supply of electric power

System and method for assigning tags to control instruction processing in a superscalar processor

Apparatus, system, and method of dynamic binary translation with translation reuse

Hardware device for processing the tasks of an algorithm in parallel

Method and apparatus for incremental commitment to architectural state in a microprocessor

Methods and apparatus for emulating software applications

Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals

Method and apparatus for clearing hazards using jump instructions

Start transactional execution (STE) instruction to support transactional program execution

Apparatus and methods for utilization of splittable execution units of a processor

Pipelined processing

Method and apparatus for avoiding read port assignment of a reorder buffer

Method and apparatus to provide a source operand for an instruction in a processor

Tightly coupled accelerator

Method for executing structured symbolic machine code on a microprocessor

Continual flow processor pipeline

Processing apparatus

Processor

Power reduction for processor front-end by caching decoded instructions

Phase adjusted delay loop executed by determining a number of NOPs based on a modulus value

Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector

Branch instruction control apparatus and control method

Computer executing instructions having embedded synchronization points

Method and apparatus for power throttling in a multi-thread processor

Efficient circuits for out-of-order microprocessors

Selective execution of deferred instructions in a processor that supports speculative execution

Multi-purpose register cache

Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction

Processor and pipeline reconfiguration control method

Computer architecture for shared memory access

System and method for handling load and/or store operations in a superscalar microprocessor

Instruction control apparatus, function unit, program conversion apparatus, and language processing apparatus

Temperature-aware steering mechanism

Mechanism for eliminating the restart penalty when reissuing deferred instructions

Cryptographic CPU architecture with random instruction masking to thwart differential power analysis

Cryptographic bus architecture for the prevention of differential power analysis

Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor

Method and apparatus for maintaining status coherency between queue-separated functional units

Cryptographic architecture with random instruction masking to thwart differential power analysis