189773 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Arrangements for executing machine instructions, e.g. instruction decode; Concurrent instruction execution, e.g. pipeline, look ahead Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
Cross-pipe serialization for multi-pipeline processor
#1802Instruction forwarding based on predication criteria
#1803Data processor with extended instruction code space including a prohibition combination pattern as a separate instruction
#1804Space efficient checkpoint facility and technique for processor with integrally indexed register mapping and free-list arrays
#1805Computer architecture with a hardware accumulator reset
#1806Out-of-order checkpoint reclamation in a checkpoint processing and recovery core microarchitecture
#1807Replay reduction by wakeup suppression using early miss indication
#1808Systems, apparatuses, and methods for performing a double blocked sum of absolute differences
#1809Efficient hardware instructions for single instruction multiple data processors
#1810Programmable power performance optimization for graphics cores
#1811Power gating functional units of a processor
#1812Pipelining out-of-order instructions
#1813Cross-pipe serialization for multi-pipeline processor
#1814Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer
#1815Instruction filtering
#1816NONTRANSACTIONAL STORE INSTRUCTION
#1817Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor
#1818Nontransactional store instruction
#1819Method for reducing memory latency in processor
#1820Multithread processor with different schedule pattern cycle state for handling interrupt processing
#1821Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media
#1822Deadlock/livelock resolution using service processor
#1823Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
#1824Method for convergence analysis based on thread variance analysis
#1825MFENCE and LFENCE micro-architectural implementation method and system
#1826CONTROLLING A SEQUENCE OF PARALLEL EXECUTIONS
#1827Thread scheduling in a system with multiple virtual machines
#1828APPARATUS AND METHOD FOR DYNAMIC ALLOCATION OF EXECUTION QUEUES
#1829Instruction and logic to perform dynamic binary translation
#1830Instruction merging optimization
#1831Instruction merging optimization
#1832Instruction merging optimization
#1833Ordering thread wavefronts instruction operations based on wavefront priority, operation counter, and ordering scheme
#1834Instruction scheduling for reducing register usage based on dependence depth and presence of sequencing edge in data dependence graph
#1835Throttling instruction issue rate based on updated moving average to avoid surges in DI/DT
#1836Instruction merging optimization
#1837Split-word memory
#1838Executing prefix code to substitute fixed operand in subsequent fixed register instruction
#1839Vector processor and vector processor processing method
#1840Out-of-order execution of bus transactions
#1841Energy efficient microprocessor platform based on instructional level parallelism
#1842Systems and methods for assigning code lines to clusters with storage and other constraints
#1843Operand special case handling for multi-lane processing
#1844Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
#1845Pre-scheduled replays of divergent operations
#1846Data processing system with latency tolerance execution
#1847Providing code sections for matrix of arithmetic logic units in a processor
#1848MFENCE and LFENCE micro-architectural implementation method and system
#1849Restoring a register renaming map
#1850SYSTEM AND METHOD FOR LONG RUNNING COMPUTE USING BUFFERS AS TIMESLICES
#1851METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR PARALLEL FUNCTIONAL UNITS IN MULTICORE PROCESSORS
#1852Prioritizing instructions based on the number of delay cycles
#1853Processing core with speculative register preprocessing in unused execution unit cycles
#1854Lookahead scanning and cracking of microcode instructions in a dispatch queue
#1855Processor with power control via instruction issuance
#1856LOW OVERHEAD OPERATION LATENCY AWARE SCHEDULER
#1857Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycle
#1858QoS based dynamic execution engine selection
#1859Computer instructions for activating and deactivating operands
#1860Entitlement vector for library usage in managing resource allocation and scheduling based on usage and priority
#1861Run time incremental compilation of script code
#1862MFENCE and LFENCE micro-architectural implementation method and system
#1863MFENCE and LFENCE micro-architectural implementation method and system
#1864System and method for reducing power requirements of microprocessors through dynamic allocation of datapath resources
#1865Temporal SIMT execution optimization through elimination of redundant operations
#1866WORD LINE LATE KILL IN SCHEDULER
#1867Floating point execution unit with fixed point functionality
#1868METHOD OF SCHEDULING A PLURALITY OF INSTRUCTIONS FOR A PROCESSOR
#1869Method, apparatus and instructions for parallel data conversions
#1870Method, apparatus and instructions for parallel data conversions
#1871Multilevel conversion table cache for translating guest instructions to native instructions
#1872Predicting out-of-order instruction level parallelism of threads in a multi-threaded processor
#1873Parallel processing computer systems with reduced power consumption and methods for providing the same
#1874Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independent
#1875Data processing system with latency tolerance execution
#1876Microprocessor systems and methods for handling instructions with multiple dependencies
#1877Global and local interconnect structure comprising routing matrix to support the execution of instruction sequences by a plurality of engines
#1878Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
#1879Method and apparatus for prioritizing processor scheduler queue operations
#1880Predicting cache misses using data access behavior and instruction address
#1881Store handling in a processor
#1882Low complexity out-of-order issue logic using static circuits
#1883Methods and apparatus for achieving thermal management using processing task scheduling
#1884Pipelined loop parallelization with pre-computations
#1885Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
#1886Method and apparatus for enhancing scheduling in an advanced microprocessor
#1887Processing long-latency instructions in a pipelined processor
#1888Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
#1889Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
#1890Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction
#1891Microprocessor systems and methods for latency tolerance execution
#1892Systems and methods for configuring load/store execution units
#1893Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file
#1894Processor with a Hybrid Instruction Queue with Instruction Elaboration Between Sections
#1895Reducing energy and increasing speed by an instruction substituting subsequent instructions with specific function instruction
#1896Processor with a coprocessor having early access to not-yet issued instructions
#1897Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is available
#1898Runtime extraction of data parallelism
#1899MFENCE and LFENCE micro-architectural implementation method and system
#1900Method and apparatus for fast decoding and enhancing execution speed of an instruction
#1901Storing in other queue when reservation station instruction queue reserved for immediate source operand instruction execution unit is full
#1902Predicting branches for vector partitioning loops when processing vector instructions
#1903Processor with power control via instruction issuance
#1904Method and apparatus for providing early bypass detection to reduce power consumption while reading register files of a processor
#1905Retrieving instructions of a single branch, backwards short loop from a virtual loop buffer
#1906MULTI-ISSUE UNIFIED INTEGER SCHEDULER
#1907Cryptographic Architecture with Instruction Masking and other Techniques for Thwarting Differential Power Analysis
#1908METHOD AND APPARATUS FOR AN ENHANCED SPEED UNIFIED SCHEDULER UTILIZING OPTYPES FOR COMPACT LOGIC
#1909Hardware device for processing the tasks of an algorithm in parallel
#1910Hardware device for processing the tasks of an algorithm in parallel
#1911Matrix algorithm for scheduling operations
#1912Thread scheduling on multiprocessor systems
#1913Scheduling scheme for load/store operations
#1914Retirement serialisation of status register access operations
#1915Scheduling execution of instructions on a processor having multiple hardware threads with different execution resources
#1916Vector processing circuit, command issuance control method, and processor system
#1917Method and apparatus for controlling a translation lookaside buffer
#1918LOAD BALANCING WHEN ASSIGNING OPERATIONS IN A PROCESSOR
#1919Clock control device, clock control method, clock control program and integrated circuit
#1920Computing device with asynchronous auxiliary execution unit
#1921Dynamic instruction splitting
#1922MICRO-OPERATION PROCESSING SYSTEM AND DATA WRITING METHOD THEREOF
#1923PROCESSOR, APPARATUS, AND METHOD FOR MEMORY MANAGEMENT
#1924PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES
#1925Allocation and control unit for controlling parallel execution of threads on auxiliary processing units
#1926Fault tolerant stability critical execution checking using redundant execution pipelines
#1927Instruction set architecture extensions for performing power versus performance tradeoffs
#1928Not-taken path instruction for selectively generating a forwarded result from a previous instruction based on branch outcome
#1929Selectively defering load instructions after encountering a store instruction with an unknown destination address during speculative execution
#1930Multithreaded clustered microarchitecture with dynamic back-end assignment
#1931Cache-based pipline control method and system with non-prediction branch processing using a track table containing program information from both paths of a branch instruction
#1932Method and system of scheduling out-of-order operations without the requirement to execute compare, ready and pick logic in a single cycle
#1933Mesochronous signaling system with clock-stopped low power mode
#1934Mesochronous signaling system with core-clock synchronization
#1935Mesochronous signaling system with multiple power modes
#1936SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATION
#1937Clock-forwarding low-power signaling system
#1938Early release of resources by proceeding to retire store operations from exception reporting stage but keeping in load/store queue
#1939Processor with cycle offsets and delay lines to allow scheduling of instructions through time
#1940System using a unique marker with each software code-block
#1941Emulating hexadecimal floating-point operations in non-native systems
#1942Precise data return handling in speculative processors
#1943Early instruction text based operand store compare reject avoidance
#1944Multiple instruction execution mode resource-constrained device
#1945Runtime extraction of data parallelism
#1946Processor and method for distributing load among plural pipeline units
#1947Sharing resources between a CPU and GPU
#1948Dual issuing of complex instruction set instructions
#1949Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
#1950Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode
#1951Method, apparatus and instructions for parallel data conversions
#1952Managing power of thread pipelines according to clock frequency and voltage specified in thread registers
#1953Multithreaded processor with plurality of scoreboards each issuing to plurality of pipelines
#1954Single instruction group information processing apparatus for dynamically performing transient processing associated with a repeat instruction
#1955Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor
#1956Optimal deallocation of instructions from a unified pick queue
#1957Dynamic selection of execution stage
#1958Processor core stacking for efficient collaboration
#1959Credit-based streaming multiprocessor warp scheduling
#1960Instructions for managing a parallel cache hierarchy
#1961Method, system and computer-accessible medium for providing a distributed predicate prediction
#1962Method and system for generating object code to facilitate predictive memory retrieval
#1963SIMD parallel computer system, SIMD parallel computing method, and control program
#1964Non-atomic scheduling of micro-operations to perform round instruction
#1965Device having multiple instruction execution modules and a management method
#1966INSTRUCTION EXECUTION CONTROL METHOD, INSTRUCTION FORMAT, AND PROCESSOR
#1967Pipe scheduling for pipelines based on destination register number
#1968Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism
#1969Dispatching instruction from reservation station to vacant instruction queue of alternate arithmetic unit
#1970CPU clock control during cache memory stall
#1971System and method for balancing instruction loads between multiple execution units using assignment history
#1972Power consumption management
#1973Vector processor with vector register file configured as matrix of data cells each selecting input from generated vector data or data from other cell via predetermined rearrangement path
#1974Result path sharing between a plurality of execution units within a processor
#1975Systems and Methods for Ramped Power State Control in a Semiconductor Device
#1976Managing instructions for more efficient load/store unit usage
#1977Loading data to vector renamed register from across multiple cache lines
#1978Processor and method for implementing instruction support for hash algorithms
#1979Routing instructions in a processor
#1980Tracking deallocated load instructions using a dependence matrix
#1981Selecting fixed-point instructions to issue on load-store unit
#1982Processor with automatic scheduling of operations
#1983Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is full
#1984Multi-processor systems communicating using data and control tokens
#1985Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus
#1986Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register
#1987MICROCOMPUTER AND DIVIDING CIRCUIT
#1988Reducing instruction collisions in a processor
#1989System and Method for Detecting and Recovering from Errors in an Instruction Stream of an Electronic Data Processing System
#1990System and method for fusing instructions queued during a time window defined by a delay counter
#1991Processor Apparatus for Executing Instructions with Local Slack Prediction of Instructions and Processing Method Therefor
#1992Instruction execution control device and instruction execution control method
#1993Processor, Method and Computer Program
#1994Multi-thread processor selecting threads on different schedule pattern for interrupt processing and normal operation
#1995Microprocessor with fused store address/store data microinstruction
#1996Scheduling control within a data processing system
#1997Processing prefix code in instruction queue storing fetched sets of plural instructions in superscalar processor
#1998Sharing pipeline by inserting NOP to accommodate memory access request received from other processors
#1999PARALLEL PROGRAM EXECUTION OF COMMAND BLOCKS USING FIXED BACKJUMP ADDRESSES
#2000Redundant execution of instructions in multistage execution pipeline during unused execution cycles
#2001Thread ordering techniques
#2002System and method for reducing power requirements of microprocessors through dynamic allocation of datapath resources
#2003Microprocessor with multiple operating modes dynamically configurable by a device driver based on currently running applications
#2004DEVICE AND METHOD FOR CONTROLLING AN INTERNAL STATE OF INFORMATION PROCESSING EQUIPMENT
#2005ESTIMATOR, TABLE MANAGING DEVICE, SELECTING DEVICE, TABLE MANAGING METHOD, PROGRAM FOR ALLOWING COMPUTER TO EXECUTE THE TABLE MANAGING METHOD, AND RECORDING MEDIUM WHERE THE PROGRAM IS RECORDED
#2006GENERATING AND PERFORMING DEPENDENCY CONTROLLED FLOW COMPRISING MULTIPLE MICRO-OPERATIONS (uops)
#2007Method and apparatus for vector execution on a scalar machine
#2008Instruction issue control wtihin a multithreaded processor
#2009Voltage droop mitigation through instruction issue throttling
#2010Vector processor system
#2011System for providing trace data in a data processor having a pipelined architecture
#2012CRYPTOGRAPHIC OPERATION PROCESSING CIRCUIT
#2013COMPUTER ARCHITECTURE
#2014Apparatus For Storing Instructions In A Multithreading Microprocessor
#2015Apparatus and method for optimizing the performance of x87 floating point addition instructions in a microprocessor
#2016Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture
#2017Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same For Use In Multithreading Microprocessor
#2018Apparatus, method and computer program for processing instruction
#2019Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
#2020Method and apparatus to improve execution of a stored program
#2021Reduced overhead address mode change management in a pipelined, recycling microprocessor
#2022Conditional execution of floating point store instruction by simultaneously reading condition code and store data from multi-port register file
#2023Supporting partial recycle in a pipelined microprocessor
#2024Selective power-down for high performance CPU/system
#2025Method, system, and computer program product for selectively accelerating early instruction processing
#2026System and method for handling load and/or store operations in a superscalar microprocessor
#2027Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration
#2028Method and system for early instruction text based operand store compare reject avoidance
#2029System and Method for Issue Schema for a Cascaded Pipeline
#2030Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor
#2031Method and system for implementing store buffer allocation
#2032Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions
#2033Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs
#2034System and method for parsing and allocating a plurality of packets to processor core threads
#2035Branch target address cache including address type tag bit
#2036Launching multiple concurrent memory moves via a fully asynchronoous memory mover
#2037Block count based procedure layout and splitting
#2038Processing unit incorporating multirate execution unit
#2039Processing Unit Incorporating Issue Rate-Based Predictive Thermal Management
#2040Apparatus, system, and method for discontiguous multiple issue of instructions
#2041Unified Processor Architecture For Processing General and Graphics Workload
#2042System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
#2043Tracking store ordering hazards in an out-of-order store queue
#2044Mechanism for soft error detection and recovery in issue queues
#2045Data processing device and control method for preventing an exception caused by an instruction sent to a peripheral device by a branch source program from occurring during execution of a branch destination program or interrupt program
#2046Multifunction hexadecimal instruction form system and program product
#2047Design structure for dynamically selecting compiled instructions
#2048PROCESSOR AND INSTRUCTION SCHEDULING METHOD
#2049Multithreaded clustered microarchitecture with dynamic back-end assignment
#2050Retrieving instructions of a single branch, backwards short loop from a local loop buffer or virtual loop buffer
#2051System and Method for Issuing Load-Dependent Instructions from an Issue Queue in a Processing Unit
#2052DATA PROCESSING APPARATUS
#2053Method and system of peak power enforcement via autonomous token-based control and management
#2054Methods and apparatus for executing or converting real-time instructions
#2055Apparatus and method of avoiding bank conflict in single-port multi-bank memory system
#2056Parallel processing computer systems with reduced power consumption and methods for providing the same
#2057Replaying memory operation assigned a load/store buffer entry occupied by store operation processed beyond exception reporting stage and retired from scheduler
#2058Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines
#2059PARALLEL PROGRAM EXECUTION OF COMMAND BLOCKS USING FIXED BACKJUMP ADDRESSES
#2060Command selection method and its apparatus
#2061PARALLEL PROCESSOR AND ARITHMETIC METHOD OF THE SAME
#2062Technique to enable store forwarding during long latency instruction execution
#2063COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION REORDER BUFFER
#2064Stall-free pipelined cache for statically scheduled and dispatched execution
#2065Intentionally delaying execution of a copy instruction to achieve simultaneous execution with a subsequent, non-adjacent write instruction
#2066Efficient memory update process for well behaved applications executing on a weakly-ordered processor
#2067Time-of-life counter for handling instruction flushes from a queue
#2068Handling data cache misses out-of-order for asynchronous pipelines
#2069Concurrent execution of instructions in a processing system
#2070Speculative code motion for memory latency hiding
#2071Methods and apparatus to selectively power functional units
#2072Adaptive allocation of reservation station entries to an instruction set with variable operands in a microprocessor
#2073Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system
#2074MULTITHREAD PROCESSOR
#2075Method, apparatus and computer program product for dynamically selecting compiled instructions
#2076Register file backup queue
#2077Mechanism for predicting and suppressing instruction replay in a processor
#2078Adaptive execution frequency control method for enhanced instruction throughput
#2079Adaptive execution cycle control method for enhanced instruction throughput
#2080High-performance, superscalar-based computer system with out-of-order instruction execution
#2081Dynamically composing processor cores to form logical processors
#2082System and method for assigning tags to control instruction processing in a superscalar processor
#2083System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
#2084Structure for a circuit function that implements a load when reservation lost instruction to perform cacheline polling
#2085Issue unit for placing a processor into a gradual slow mode of operation
#2086Age matrix for queue entries dispatch order
#2087Age matrix for queue dispatch order
#2088AGE MATRIX FOR QUEUE DISPATCH ORDER
#2089MICROCOMPUTER AND DIVIDING CIRCUIT
#2090Unified Cascaded Delayed Execution Pipeline for Fixed and Floating Point Instructions
#2091Data processing apparatus and method for reducing issue circuitry responsibility by using a predetermined pipeline stage to schedule a next operation in a sequence of operations defined by a complex instruction
#2092Method and system for altering processor execution of a group of instructions
#2093Method and Device for Separating the Processing of Program Code in a Computer System Having at Least Two Execution Units
#2094Store handling in a processor
#2095Method to Detect a Stalled Instruction Stream and Serialize Micro-Operation Execution
#2096Memory Subsystem having a Multipurpose Cache for a Stream Graphics Multiprocessor
#2097Minimizing unscheduled D-cache miss pipeline stalls in a cascaded delayed execution pipeline
#2098Method and apparatus for register renaming
#2099SIMPLE LOAD AND STORE DISAMBIGUATION AND SCHEDULING AT PREDECODE
#2100Simple load and store disambiguation and scheduling at predecode