189794 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Arrangements for executing machine instructions, e.g. instruction decode; Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
Sub-classes:USER PREFERENCE OPTIMIZED BASIC INPUT/OUTPUT SYSTEM CONFIGURATION VIA A RETRIEVAL-AUGMENTED GENERATION BASED SERVICE OR APPLICATION
#2LOCATION AGNOSTIC DATA ACCESS
#3METHOD AND SYSTEM TO SUPPORT DATA STREAMING FOR MATRIX OPERATIONS VIA A MACHINE LEARNING HARDWARE
#4STREAMING ENGINE FOR MACHINE LEARNING ARCHITECTURE
#5PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS
#6EXECUTABLE COMMAND SECURITY
#7DYNAMICALLY EXECUTING DATA SOURCE AGNOSTIC DATA PIPELINE CONFIGURATIONS
#8LOCATION AGNOSTIC DATA ACCESS
#9Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
#10CI/CD pipeline to container conversion
#11Supporting instruction set architecture components across releases
#12Virtual machine for virtualizing graphics functions
#13Coprocessor context priority
#14Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
#15Apparatuses, methods, and systems for instructions for operating system transparent instruction state management of new instructions for application threads
#16ACCELERATING NETWORK SECURITY MONITORING
#17SYSTEM AND METHODS FOR RECONSTITUTING AN OBJECT IN A RUNTIME ENVIRONMENT USING HEAP MEMORY
#18Electronic devices generating verification vector for verifying semiconductor circuit and methods of operating the same
#19Microcontroller architecture for non-volatile memory
#20Microcontroller architecture for non-volatile memory
#21Systems and methods for simulation of dynamic systems
#22Securing microprocessors against information leakage and physical tampering
#23Enabling parallel memory accesses by providing explicit affine instructions in vector-processor-based devices
#24Architecture of crossbar of inference engine
#25Streaming engine for machine learning architecture
#26Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine
#27Apparatus and method for protecting program memory for processing cores in a multi-core integrated circuit
#28Microcontroller architecture for non-volatile memory
#29Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
#30Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
#31Securing microprocessors against information leakage and physical tampering
#32Policies for shader resource allocation in a shader core
#33Flexible shader export design in multiple computing cores
#34Data processing
#35Computer instruction processing method, coprocessor, and system
#36Method and device for synthesizing a circuit layout
#37Unified register file for supporting speculative architectural states
#38Graphics processing
#39Processor with an expandable instruction set architecture for dynamically configuring execution resources
#40Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
#41Hardware accelerated conversion system using pattern matching
#42Apparatus and method for low-latency invocation of accelerators
#43Apparatus and method for low-latency invocation of accelerators
#44Central processing unit with enhanced instruction set
#45Apparatus and method for low-latency invocation of accelerators
#46Hardware interface component for processing write access requests that identify a register using lesser significant bits of a target address and identify an arithmetic operation to be performed using greater significant bits of the target address
#47Cache memory apparatus
#48Trace buffer based replay for context switching
#49Computer system including reconfigurable arithmetic device with network of processor elements
#50Securing microprocessors against information leakage and physical tampering
#51Kick-started run-to-completion processor having no instruction counter
#52Framework to provide time bound execution of co-processor commands
#53Framework to provide time bound execution of co-processor commands
#54Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
#55Hardware accelerator configuration by a translation of configuration data
#56Apparatus and method for low-latency invocation of accelerators
#57Selection of a primary microprocessor for initialization of a multiprocessor system
#58Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
#59Vector processing in an active memory device
#60Predication in a vector processor
#61Vector processing in an active memory device
#62Predication in a vector processor
#63Memory controllers
#64Method of securing non-native code
#65Cache memory apparatus
#66Power-efficient interaction between multiple processors
#67Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
#68Policies for Shader Resource Allocation in a Shader Core
#69Securing microprocessors against information leakage and physical tampering
#70Saving and Restoring Non-Shader State Using a Command Processor
#71Processor for enabling inter-sequencer communication following lock competition and accelerator registration
#72Mapping of guest instruction block assembled according to branch prediction to translated native conversion block
#73Active memory command engine and method
#74Programmable cryptographic integrated circuit
#75Microprocessor for executing byte compiled java code
#76SYSTEMS AND METHODS INTEGRATING BOOLEAN PROCESSING AND MEMORY
#77Intermediate language accelerator chip
#78Apparatus and method for selectable hardware accelerators
#79Intermediate Language Accelerator Chip
#80Intermediate Language Accelerator Chip
#81Intermediate Language Accelerator Chip
#82Programmable integrated processor blocks
#83APPARATUS, METHOD, AND SYSTEM FOR IMPROVING POWER, PERFORMANCE EFFICIENCY BY COUPLING A FIRST CORE TYPE WITH A SECOND CORE TYPE
#84Cache memory apparatus having internal ALU
#85GPU work creation and stateless graphics in OPENGL
#86State objects for specifying dynamic state
#87Information processing apparatus and exception control circuit
#88Microprocessor for executing byte compiled JAVA code
#89Apparatus and method for enabling inter-sequencer communication following lock competition and accelerator registration
#90Hardware Function Generator Support in a DSP
#91Internal, processing-unit memory for general-purpose use
#92Selectively adjusting CPU wait mode based on estimation of remaining work before task completion on GPU
#93Computer system including reconfigurable arithmetic device with network of processor elements
#94PARALLEL OPERATION DEVICE ALLOWING EFFICIENT PARALLEL OPERATIONAL PROCESSING
#95Active memory command engine and method
#96Controller which controls operation of nonvolatile semiconductor memory and semiconductor memory device including nonvolatile semiconductor memory and controller therefore
#97Computing apparatus and method of handling interrupt
#98Data moving processor
#99Multiprocessor system
#100Method for manipulating data in a group of processing elements to perform a reflection of the data
#101Slave and a master device, a system incorporating the devices, and a method of operating the slave device
#102Multi-chip rendering with state control
#103Microcontroller based flash memory digital controller system
#104Semiconductor device and data processing method performed by semiconductor device to perform a repeat operation within a reconfigurable pipeline
#105Data processing apparatus having address conversion circuit
#106Multi-cluster dynamic reconfigurable circuit for context valid processing of data by clearing received data with added context change indicative signal
#107Apparatus and method for selectable hardware accelerators in a data driven architecture
#108System, method and apparatus for memory with embedded associative section for computations
#109Method and Apparatus for Loading Data and Instructions Into a Computer
#110SIMD processor performing fractional multiply operation with saturation history data processing to generate condition code flags
#111Microprocessor with program-accessible re-writable non-volatile state embodied in blowable fuses of the microprocessor
#112Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor
#113Off-line task list architecture utilizing tightly coupled memory system
#114Apparatus for and method of processor to processor communication for coprocessor functionality activation
#115Method, system and computer program product for storing external device result data
#116Obtaining data in a pipelined processor
#117CO-PROCESSOR FOR STREAM DATA PROCESSING
#118Move Facility and Instructions Therefore
#119HANDSHAKING DUAL-PROCESSOR ARCHITECTURE OF DIGITAL CAMERA
#120HARDWARE IMPLEMENTATION OF THE SECURE HASH STANDARD
#121Unified Processor Architecture For Processing General and Graphics Workload
#122Controlling cleaning of data values within a hardware accelerator
#123Short-circuit evaluation of Boolean expression by rolling up sub-expression result in registers storing default value
#124Method and system for power-state transition controllers
#125CONTROL SYSTEM WITH MULTIPLE PROCESSORS AND CONTROL METHOD THEREOF
#126MULTIPROCESSING DEVICE AND INFORMATION PROCESSING DEVICE
#127Communication paths for enabling inter-sequencer communication following lock competition and accelerator registration
#128Dispatch mechanism for dispatching instructions from a host processor to a co-processor
#129Processor, virtual memory system, and virtual storing method
#130Information processing apparatus and exception control circuit
#131Shared readable and writeable global values in a graphics processor unit pipeline
#132Methods and apparatus performing hash operations in a cryptography accelerator
#133Data transfer system, data transfer method, host apparatus and image forming apparatus
#134Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating system
#135Removable computer with mass storage
#136Removable computer with mass storage
#137Active memory command engine and method
#138Processing function connected to processor memory hierarchy
#139Process for running programs on processors and corresponding processor system
#140Add-subtract coprocessor instruction execution on complex number components with saturation and conditioned on main processor condition flags
#141Programming environment for heterogeneous processor resource integration
#142Semiconductor device
#143INSTRUCTION COMMUNICATION TECHNIQUES FOR MULTI-PROCESSOR SYSTEM
#144Graphic processor and information processing device
#145Storing and processing SIMD saturation history flags and data size
#146Security message authentication instruction
#147Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques
#148Information processing apparatus, information processing method and computer program
#149Synchronizing a plurality of processors
#150Modular distributive arithmetic logic unit
#151Method for processing multiple operations
#152Boolean Processor
#153Programmable video signal processor for video compression and decompression
#154Accelerator load balancing with dynamic frequency and voltage reduction
#155Cryptographic device employing parallel processing
#156Securing microprocessors against information leakage and physical tampering
#157EMBEDDED SYSTEM AND OPERATING METHOD THEREOF
#158METHODS AND APPARATUS TO IMPLEMENT HIGH-PERFORMANCE COMPUTING
#159Coupling a general purpose processor to an application specific instruction set processor
#160Transferring data between registers in a RISC microprocessor architecture
#161Inter-processor communication method
#162Memory Controller for Sparse Data Computation System and Method Therefor
#163Using breakpoints for debugging in a RISC microprocessor architecture
#164Overlapping command at one stage submitting method of dynamic cycle pipeline
#165Floating point exception handling in a risc microprocessor architecture
#166Using trap routines in a RISC microprocessor architecture
#167Method and device for protected transmission of data words
#168System and method for fine-grain instruction parallelism for increased efficiency of processing compressed multimedia data
#169Parallel operation device allowing efficient parallel operational processing
#170Off-board computational resources
#171Microcontroller based flash memory digital controller system
#172Handling address translations and exceptions of a heterogeneous resource of a processor using another processor resource
#173Method and device for protected transmission of data words
#174METHOD AND APPARATUS FOR INTERFACING A PROCESSOR AND COPROCESSOR
#175Hardware JavaTM Bytecode Translator
#176Highly integrated multiprocessor system
#177Management of access to data from memory
#178OPTIMIZATION OF SUBSYSTEM INTERCONNECTIONS IN AN ELECTRONIC DEVICE
#179Method, system and computer program product for efficiently utilizing limited resources in a graphics device
#180Multi-graphics processor system, graphics processor and data transfer method
#181Detecting the boundaries of memory in a RISC microprocessor architecture
#182Availability of space in a RISC microprocessor architecture
#183Method and apparatus for image blending
#184Method and system for trace generation using memory index hashing
#185Instruction subgraph identification for a configurable accelerator
#186Computational fluid dynamics (CFD) coprocessor-enhanced system and method
#187Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values
#188CPU datapipe architecture with crosspoint switch
#189Graphics processing unit used for cryptographic processing
#190Firmware socket module for FPGA-based pipeline processing
#191Microprocessor for executing byte compiled JAVA code
#192DUAL-PROCESSOR COMPLEX DOMAIN FLOATING-POINT DSP SYSTEM ON CHIP
#193Multi-core multi-thread processor
#194Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
#195System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values
#196DSP System With Multi-Tier Accelerator Architecture and Method for Operating The Same
#197Methods and system for managing computational resources of a coprocessor in a computing system
#198Processor apparatus including specific signal processor core capable of dynamically scheduling tasks and its task control method
#199Atomic operation involving processors with different memory transfer operation sizes
#200Active memory command engine and method
#201Java hardware accelerator using microcode engine
#202GPU internal wait/fence synchronization method and apparatus
#203Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content
#204Loop data processing system and method for dividing a loop into phases
#205GPU pipeline multiple level synchronization controller processor and method
#206Graphics input command stream scheduling method and apparatus
#207GPU pipeline synchronization and control system and method
#208Universal embedded controller for freeing CPU from operations of peripheral subsystem units with table of functions including an instruction specifying battery controller select protocol
#209Method and apparatus for software-assisted data cache and prefetch control
#210Method and system for audio signal processing for Bluetooth wireless headsets using a hardware accelerator
#211Offload system, method, and computer program product for port-related processing
#212Data reordering processor and method for use in an active memory device
#213Information processing apparatus and program for causing computer to execute power control method
#214Emulator and emulating method for adjusting the execution timing of instructions included in an application to be emulated
#215Configurable processor architecture for use in multi-standard communications
#216Processor, virtual memory system, and virtual storing method
#217Hardware function generator support in a DSP
#218Stream processor including DMA controller used in data processing apparatus
#219Command execution controlling apparatus, command execution instructing apparatus and command execution controlling method
#220Software defined FIFO memory for storing a set of data from a stream of source data
#221Data processing system
#222Flexible power reduction for embedded components
#223Active memory data compression system and method
#224Java virtual machine hardware for RISC and CISC processors
#225Information processing device, information processing method, semiconductor device, and computer program for executing instructions by using a plurality of processors
#226Identifying and processing essential and non-essential code separately
#227Method and apparatus for pipelined processing of data packets
#228Method and apparatus for image blending
#229Apparatus and method for matrix data processing
#230Semiconductor integrated circuit
#231Semiconductor signal processing device
#232Software package definition for PPU enabled system
#233Event counter and signaling co-processor for a network processor engine
#234Programmable graphics processing engine
#235DSP processor architecture with write datapath word conditioning and analysis
#236Hardware accelerator for an object-oriented programming language
#237Security chip architecture and implementations for cryptography acceleration
#238Video image processing with parallel processing
#239Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements
#240Multiple-core processor with support for multiple virtual processors
#241Semiconductor device
#242Apparatus and method for interconnecting a processor to co-processors using shared memory
#243Integrated circuit with a plurality of host processor family types
#244Loosely-biased heterogeneous reconfigurable arrays
#245Algorithm mapping, specialized instructions and architecture features for smart memory computing
#246Method for using multiple processing resources which share multiple co-processor resources
#247Interface for integrating reconfigurable processors into a general purpose computing system
#248Bus control system for integrated circuit device with improved bus access efficiency
#249Parallel vector processing
#250Application program execution enhancing instruction set generation for coprocessor and code conversion with marking for function call translation
#251System and method for performing security operations on network data
#252Coupling GP processor with reserved instruction interface via coprocessor port with operation data flow to application specific ISA processor with translation pre-decoder
#253Method for transferring data in a multiprocessor system, multiprocessor system and processor carrying out this method
#254Array—type computer processor with reduced instruction storage
#255Java hardware accelerator using microcode engine
#256Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques
#257Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques
#258Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques
#259Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques
#260Tightly coupled and scalable memory and execution unit architecture
#261Highly programmable MAC architecture for handling protocols that require precision timing and demand very short response times
#262System and method for performing matrix operations
#263Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle
#264Distributed processor memory module and method
#265Saturated arithmetic in a processing unit
#266Providing a register file memory with local addressing in a SIMD parallel processor
#267Method and system for in-line data conversion outside of a machine learning hardware
#268Methods and apparatus for automatically transforming software process recordings into dynamic automation scripts
#269Method and apparatus for performing machine learning operations in parallel on machine learning hardware
#270Method and apparatus for performing machine learning operations in parallel on machine learning hardware
#271Coprocessor context priority
#272ROM-code programmable digital signal processor
#273Active memory data compression system and method