189795 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Arrangements for executing machine instructions, e.g. instruction decode; Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set Arrangements for communication of instructions and data
Apparatus and Method for Remote Atomic Floating Point Operations
#2Coprocessor Prefetcher
#3STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART
#4ACCELERATOR CONTROL SYSTEM, ACCELERATOR CONTROL METHOD AND ACCELERATOR CONTROL PROGRAM
#5Coprocessor prefetcher
#6ELECTRONIC APPARATUS AND METHOD FOR REDUCING NUMBER OF COMMANDS
#7ELECTRONIC APPARATUS AND METHOD FOR REDUCING NUMBER OF COMMANDS
#8Coprocessor prefetcher
#9Graphics processing unit systems for performing data analytics operations in data science
#10Inter-core data processing method, system on chip and electronic device
#11Coprocessor context priority
#12Reducing a number of commands transmitted to a co-processor by merging register-setting commands having address continuity
#13COMPUTING MACHINE, METHOD AND NON-TRANSITORY COMPUTER-READABLE MEDIUM
#14Streaming engine with error detection, correction and restart
#15Microprocessor with high-efficiency decoding of complex instructions
#16Method and apparatus for balancing binary instruction burstization and chaining
#17System and method for physically separating, across different processing units, software for handling exception causing events from executing program code
#18Overlay layer for network of processor cores
#19Streaming engine with error detection, correction and restart
#20Non-transitory computer readable storage medium storing set of program instructions for controlling information processing apparatus to function as higher-level module and lower-level module
#21Parallelization of numeric optimizers
#22Exit history based branch prediction
#23Data processing apparatus that switches to execution of a different command list at a preset control point, method of controlling the same, and computer-readable storage medium
#24Parallelization of numeric optimizers
#25Function evaluation using multiple values loaded into registers by a single instruction
#26Estimating performance of GPU application for different GPU-link performance ratio
#27Input-output processing on a remote integrated circuit chip
#28Memory unit and method of operation of a memory unit to handle operation requests
#29Streaming engine with error detection, correction and restart
#30Programmable radio transceivers
#31Machine intelligence and learning for graphic chip accessibility and execution
#32Main processor prefetching operands for coprocessor operations
#33Neural network unit
#34Communicating via a mailbox interface of a processor
#35System, apparatus and method for low overhead control transfer to alternate address space in a processor
#36Radix sort acceleration using custom asic
#37Processor, accelerator, and direct memory access controller within a core reading/writing local synchronization flag area for parallel
#38Data format conversion apparatus and method and buffer chip
#39Streaming engine with error detection, correction and restart
#40Apparatus and method for accelerating operations in a processor which uses shared virtual memory
#41External intrinsic interface
#42Computing system and method employing processing of operation corresponding to offloading instructions from host processor by memory's internal processor
#43Apparatus and method for low-latency invocation of accelerators
#44Apparatus and method for low-latency invocation of accelerators
#45Apparatus and method for accelerating operations in a processor which uses shared virtual memory
#46Context switching mechanism for a processor having a general purpose core and a tightly coupled accelerator
#47Hardware instruction generation unit for specialized processors
#48Apparatus and method for low-latency invocation of accelerators
#49Hardware interface component for processing write access requests that identify a register using lesser significant bits of a target address and identify an arithmetic operation to be performed using greater significant bits of the target address
#50Processing video content
#51Radix sort acceleration using custom ASIC
#52Function evaluation using multiple values loaded into registers by a single instruction
#53Computer accelerator system using a trigger architecture memory access processor
#54Radix sort acceleration using custom ASIC
#55Control device and access system utilizing the same
#56Method, apparatus and system for data stream processing with a programmable accelerator
#57Command instruction management
#58Context switching mechanism for a processing core having a general purpose CPU core and a tightly coupled accelerator
#59Apparatus and method for memory-hierarchy aware producer-consumer instruction
#60Apparatus and method for low-latency invocation of accelerators
#61Programmable hardware accelerators in CPU
#62Method and device for passing parameters between processors
#63Hardware-base accelerator for managing copy-on-write of multi-level caches utilizing block copy-on-write differential update table
#64Apparatus and method for accelerating operations in a processor which uses shared virtual memory
#65Synchronous software interface for an accelerated compute engine
#66Parallel processing device
#67External auxiliary execution unit interface for format conversion of instruction from issue unit to off-chip auxiliary execution unit
#68Infrastructure support for accelerated processing device memory paging without operating system integration
#69Co-processing acceleration method, apparatus, and system
#70DE-COUPLED CO-PROCESSOR INTERFACE
#71Processor for enabling inter-sequencer communication following lock competition and accelerator registration
#72External intrinsic interface
#73METHOD FOR REORDERING THE REQUEST QUEUE OF A HARDWARE ACCELERATOR
#74Hardware accelerator module and method for setting up same
#75Method macro expander
#76SEMICONDUCTOR CIRCUIT AND DESIGNING APPARATUS
#77METHOD AND SYSTEM FOR REORDERING THE REQUEST QUEUE OF A HARDWARE ACCELERATOR
#78Reducing remote reads of memory in a hybrid computing environment
#79Processor, co-processor, information processing system, and method for controlling processor, co-processor, and information processing system
#80Apparatus and method for enabling inter-sequencer communication following lock competition and accelerator registration
#81Method and system for loading application to a local memory of a co-processor system by using position independent loader
#82Method and structure of using SIMD vector architectures to implement matrix multiplication
#83Apparatus for controlling NAND flash memory
#84Communication paths for enabling inter-sequencer communication following lock competition and accelerator registration
#85Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
#86Methods and apparatus for interfacing between a host processor and a coprocessor
#87System and method for cryptography processing units and multiplier
#88Coprocessor processing instructions in turn from multiple instruction ports coupled to respective processors
#89Method and apparatus for interfacing a processor to a coprocessor
#90Coprocessor bus architecture
#91Coprocessor instruction loading from port register based on interrupt vector table indication
#92Coprocessor context priority
#93Graphics processing unit systems for performing data analytics operations in data science
#94State machine communication
#95Computer vision processing in hardware data paths
#96Flexibly deriving intended thread data exchange patterns
#97Core for controlling multiple serial peripheral interfaces (SPI's)
#98Computer vision processing in hardware data paths