199446 ⎘
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect Auxiliary circuits
Sub-classes:MEMORY DEVICE WITH SOURCE LINE CONTROL
#2Circuits with Charge Trapping Transistors
#3MULTI-LEVEL MEMRISTOR ELEMENTS
#4Semiconductor circuit including latch circuit for error correction
#5Multi-level memristor elements
#6Memory device with source line control
#7Multiferroic memory with piezoelectric layers and related methods
#8Memory device with source line control
#9Non-volatile memory devices and systems with volatile memory features and methods for operating the same
#10Magnetic device and arithmetic device
#11Apparatus and method for endurance of non-volatile memory banks via wear leveling with linear indexing
#12Magnetic memory
#13Magnetic memory device
#14Magnetoresistance effect element and magnetic memory
#15Magnetic tunnel junction devices including a free magnetic trench layer and a planar reference magnetic laver
#16Magnetoresistive memory device including a plurality of reference layers
#17Non-volatile memory devices and systems with volatile memory features and methods for operating the same
#18Multi-level memristor elements
#19Spin current magnetization rotational element, magnetoresistance effect element, and magnetic memory
#20Memory device
#21Magnetic memory
#22Multi-level memristor elements
#23Strong arm latch with wide common mode range
#24Spin current magnetization rotational element, magnetoresistance effect element, and magnetic memory
#25Magnetoelectric spin orbit logic based full adder
#26Magnetoelectric spin orbit logic based minority gate
#27Single-poly non-volatile memory cell and operating method thereof
#28Random bit cell with memory units
#29Magnetic storage device
#30STT-MRAM failed address bypass circuit and STT-MRAM device including same
#31Weight matrix circuit and weight matrix input circuit
#32Non-volatile memory devices and systems with volatile memory features and methods for operating the same
#33Initialization process for magnetic random access memory (MRAM) production
#34Magnetic device and manufacturing method of magnetic device
#35Adjustable current selectors
#36Method for stabilizing spin element and method for manufacturing spin element
#37Magnetic memory devices
#38Spin transfer torque magnetic random access memory for supporting operational modes with mode register
#39Initialization process for magnetic random access memory (MRAM) production
#40Data storage devices and methods of manufacturing the same
#41Magnetic memory device
#42Spin current magnetization rotational element, magnetoresistance effect element, and magnetic memory
#43Magnetic memory device
#44Magnetic memory devices based on 4D and 5D transition metal perovskites
#45Composite free layer for magnetoresistive random access memory
#46Non-volatile memory devices including integrated ballast resistor
#47Semiconductor memory device
#48Method for controlling a semiconductor memory device
#49Spin orbit torque (SOT) MRAM having a source line connected to a spin orbit conductive layer and arranged above a magnetoresistive element
#50Magnetic memory device
#51METHOD AND SYSTEM FOR PROVIDING A DUAL MAGNETIC JUNCTION HAVING MITIGATED FLOWERING FIELD EFFECTS
#52Memory device having source contacts located at intersections of linear portions of a common source, electronic systems, and associated methods
#53Magnetic memory device
#54Spin accumulation torque MRAM
#55Electronic device and method for fabricating the same
#56Electronic device
#57Memory device with a low-current reference circuit
#58SHARED SOURCE LINE ARCHITECTURES OF PERPENDICULAR HYBRID SPIN-TORQUE TRANSFER (STT) AND SPIN-ORBIT TORQUE (SOT) MAGNETIC RANDOM ACCESS MEMORY
#59Three dimension integrated circuits employing thin film transistors
#60Logic circuits including magnetic tunnel junction devices
#61Electronic device includes resistive storage cells and reference resistance transistor, a resistance adjustment block to adjust the resistance value depending on a temperature and a data sensing block to sense the resistive value of the resistive storage cell and the reference transistor resistance value
#62Method and system for providing a diluted free layer magnetic junction usable in spin transfer torque applications
#63High efficiency spin torque switching using a ferrimagnet
#64Modular magnetoresistive memory
#65Techniques to improve switching probability and switching speed in SOT devices
#66MAGNETIC STORAGE DEVICE AND MANUFACTURING METHOD OF MAGNETIC STORAGE DEVICE
#67Magnetic storage device with a wiring having a ferromagnetic layer
#68Semiconductor memory device and method of controlling semiconductor memory device
#69Magnetic memory devices
#70Memory device based on domain wall memory and reading and writing method thereof, and apparatus for digital signal processing using the same
#71Low-layer memory for a computing platform
#72MAGNETIC TUNNEL JUNCTION DEVICE AND SEMICONDUCTOR MEMORY DEVICE
#73High speed sense amplifier latch with low power rail-to-rail input common mode range
#74Memory device
#75Memory device
#76Magnetic tunnel junction switching assisted by temperature-gradient induced spin torque
#77Spin transistor memory
#78Pattern matching device
#79Modular magnetoresistive memory
#80Magnetic memory cells with high write current and read stability
#81High sensing margin magnetic resistive memory device in which a memory cell read and write select transistors to provide different read and write paths
#82Spin orbit and spin transfer torque-based spintronics devices
#83Magnetic memory device and magnetic storage method
#84Systems and methods for implementing efficient magnetoelectric junctions
#85Magnetic memory and semiconductor-integrated-circuit
#86Physically uncloneable function device using MRAM
#87Magnetic device with spin polarisation
#88Memory devices and related methods
#89Magnetic memory
#90Latch offset cancelation for magnetoresistive random access memory
#91Magnetic logic device, magnetic logic circuit, and magnetic memory
#92SEMICONDUCTOR DEVICE
#93Memory device
#94Differential magnetic tunnel junction pair including a sense layer with a high coercivity portion
#95ELECTRONIC DEVICE
#96Circuit and method for accessing a bit cell in a spin-torque MRAM
#97Multi-bit magnetic memory cell
#98Precessional magnetization reversal in a magnetic tunnel junction with a perpendicular polarizer
#99Oxide interface displaying electronically controllable ferromagnetism
#100Voltage-switched magnetic random access memory (MRAM) and method for using the same
#101Semiconductor resistive memory devices including separately controllable source lines
#102Semiconductor memory device
#103MRAM with magnetic material surrounding contact plug
#104Memory device with resistance-change type storage elements
#105Three dimension integrated circuits employing thin film transistors
#106Electronic device
#107Apparatus and method for improving data storage by data inversion
#108Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read current
#109Nonvolatile memory device and method of erasing nonvolatile memory device
#110Erase method of nonvolatile memory device and storage device employing the same
#111Electronic apparatus
#112Non-volatile memory device
#113Memory devices and related methods
#114Field programming method for magnetic memory devices
#115BOOSTER CIRCUIT
#116Semiconductor intergrated circuit and operating method thereof
#117Nonvolatile memory apparatus for controlling a voltage level of enabling a local switch
#118MAGNETO-RESISTIVE EFFECT ELEMENT
#119Semiconductor memory device
#120Magnetic memory
#121MRAM self-repair with BIST logic
#122Spin transfer MRAM element having a voltage bias control
#123Nonvolatile memory apparatus having magnetoresistive memory elements and method for driving the same
#124Semiconductor device having stacked chips
#125Reference cell repair scheme
#126MRAM word line power control scheme
#127Memory devices, circuits and, methods that apply different electrical conditions in access operations
#128Semiconductor memory device having resistive memory cells and method of testing the same
#129MAGNETIC RANDOM ACCESS MEMORY
#130Method for screening arrays of magnetic memories
#131Method for magnetic screening of arrays of magnetic memories
#132Spin transfer torque magnetic random access memory for supporting operational modes with mode register
#133Semiconductor integrated circuit for low and high voltage operations
#134Nonvolatile latch circuit
#135Circuit and method for spin-torque MRAM bit line and source line voltage regulation
#136Method for magnetic screening of arrays of magnetic memories
#137Nonvolatile memory apparatus having magnetoresistive memory elements and method for driving the same
#138Semiconductor intergrated circuit and operating method thereof
#139Semiconductor memory device
#140Magnetic random access memory (MRAM) layout with uniform pattern
#141Semiconductor integrated circuit for low and high voltage operations
#142Method and system for providing a magnetic field aligned spin transfer torque random access memory
#143Software programmable logic using spin transfer torque magnetoresistive devices
#144Magnetoresistive device
#145Modular magnetoresistive memory
#146Software programmable logic using spin transfer torque magnetoresistive devices
#147Modular magnetoresistive memory
#148Software programmable logic using spin transfer torque magnetoresistive random access memory
#149Random swap injection
#150Apparatus and method for endurance of non-volatile memory banks via wear leveling and outlier compensation
#151Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection
#152Methods and apparatus for three-dimensional non-volatile memory
#153Adjustable current selectors
#154Method and system for providing a low moment free layer magnetic junction usable in spin transfer torque applications
#155Shared built-in self-analysis of memory systems employing a memory array tile architecture
#156Magnetic random access memory (MRAM) and method of operation