199453 ⎘
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect; Auxiliary circuits Verifying circuits or methods
MAGNETIC MEMORY DEVICE
#2MEMORY DEVICE WHICH GENERATES OPTIMAL WRITE VOLTAGE BASED ON REFERENCE RESISTANCE OF MEMORY CELL AND METHOD OF OPERATING THE SAME
#3LOW ERROR RATE READ OPERATION IN MULTI-MODULE ARRAYS
#4MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM)
#5APPARATUS AND METHODS FOR MANAGING SELECTOR DEVICE THRESHOLD VOLTAGE DRIFT
#6SEMICONDUCTOR STORAGE DEVICE
#7ELECTRONIC DEVICE
#8MEMORY SYSTEM AND OPERATING METHOD
#9EXTERNAL MAGNETIC FIELD DETECTION FOR MRAM DEVICE
#10MEMORY DEVICE AND MEMORY SYSTEM
#11Magnetoresistive random access memory with data scrubbing
#12SEMICONDUCTOR DEVICE, AND METHOD FOR OPERATING THE SAME
#13Magnetoresistive random access memory (MRAM) with end of life margin sensor
#14Secure wear levelling of non-volatile memory based on Galois field circuit
#15Partial pulse pairing for improved read signal quality
#16NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE
#17EXTERNAL MAGNETIC FIELD DETECTION FOR MRAM DEVICE
#18Sense amplifier structure for non-volatile memory with neighbor bit line local data bus data transfer
#19Magnetic storage device and control method of magnetic storage device
#20Magnetoresistive random access memory for physically unclonable function technology and associated random code generating method
#21Forming control method applied to resistive random-access memory cell array
#22Semiconductor device and semiconductor system
#23Memory device which generates improved read current according to size of memory cell
#24Selective reading of memory with improved accuracy
#25MRAM access coordination systems and methods via pipeline in parallel
#26Method of programming nonvolatile memory device including reversible resistance device
#27Memory device with on-chip sacrificial memory cells
#28Ramp write techniques
#29Error cache system with coarse and fine segments for power optimization
#30Magnetic storage device and control method of magnetic storage device
#31Memory devices with improved refreshing operation
#32Semiconductor device
#33Resistance change memory device and associated methods
#34Error recovery in magnetic random access memory after reflow soldering
#35Selective reading of memory with improved accuracy
#36Storage device and method of operating the same
#37Memory circuit and semiconductor device
#38Semiconductor device
#39Error cache system with coarse and fine segments for power optimization
#40Memory devices with improved refreshing operation
#41MRAM noise mitigation for write operations with simultaneous background operations
#42Bi-polar write scheme
#43Determining an inactive memory bank during an idle memory cycle to prevent error cache overflow
#44Error cache segmentation for power reduction
#45Apparatus for low power write and read operations for resistive memory
#46MEMORY DEVICE WITH SOFT-DECISION DECODING AND METHODS OF READING AND FORMING THEREOF
#47Apparatus including magnetoresistive memory device
#48MRAM access coordination systems and methods with a plurality of pipelines
#49Memory device
#50Magnetic memory device and writing method that achieves different resistance states with unidirectional voltages
#51Multi-port random access memory
#52Computational accuracy in a crossbar array
#53Multi-chip module for MRAM devices with levels of dynamic redundancy registers
#54Nonvolatile memory device and operating method thereof
#55WRITE VERIFY PROGRAMMING OF A MEMORY DEVICE
#56Method of optimizing write voltage based on error buffer occupancy
#57On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects
#58METHODS AND DEVICES FOR HEALING RESET ERRORS IN A MAGNETIC MEMORY
#59Bad bit register for memory
#60Bad bit register for memory
#61Apparatus for low power write and read operations for resistive memory
#62Write algorithm for memory to reduce failure rate of write operations
#63Screening method for magnetic storage device, screening apparatus for magnetic storage device, and manufacturing method of magnetic storage device
#64Magnetoresistive memory device
#65Resistance change type memory including write control circuit to control write to variable resistance element
#66Smart cache design to prevent overflow for a memory device with a dynamic redundancy register
#67Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers
#68Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers
#69Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device
#70Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank
#71Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register
#72Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device
#73Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operation
#74Method of reading data from a memory device using multiple levels of dynamic redundancy registers
#75Device with dynamic redundancy registers
#76Controlling write pulse width to non-volatile memory based on free space of a storage
#77Semiconductor memory system and operating method thereof
#78Memory devices with improved refreshing operation
#79Memory device and memory system
#80Data-write device for resistance-change memory element
#81Method and apparatus for bipolar memory write-verify
#82Selective reading of memory with improved accuracy
#83Multibit self-reference thermally assisted MRAM
#84Write verify programming of a memory device
#85NONVOLATILE RAM
#86Magnetic storage cell memory with back hop-prevention
#87Method and apparatus for bipolar memory write-verify
#88Memory device and method for correcting a stored bit sequence
#89Robust slope detection technique for STTRAM and MRAM sensing
#90Memory devices with improved refreshing operation
#91Advanced programming verification schemes for memory cells
#92Nonvolatile memory
#93Semiconductor memory apparatus
#94Apparatuses and methods for sensing using an integration component
#95Memory control circuit, cache memory and memory control method
#96Unipolar-switching perpendicular MRAM and method for using same
#97Apparatus for low power write and read operations for resistive memory
#98Resistive memory device, resistive memory system, and method of operating resistive memory device
#99Nonvolatile semiconductor storage device and rewriting method thereof
#100Write verify programming of a memory device
#101Semiconductor memory, memory system and method of controlling semiconductor memory
#102Nonvolatile semiconductor memory device
#103Resistive memory device having memory cell arrays with multiple stack layers and bad-region managing circuit and method for managing short failure
#104Memory devices with improved refreshing operation
#105Resistive memory device capable of increasing sensing margin by controlling interface states of cell transistors
#106MRAM smart bit write algorithm with error correction parity bits
#107Non-volatile memory validity
#108Magnetic-domain-wall-displacement memory cell and initializing method therefor
#109Selective reading of memory with improved accuracy
#110Advanced programming verification schemes for memory cells
#111Resistive memory device capable of increasing sensing margin by controlling interface states of cell transistors
#112Stabilization of resistive memory
#113Pulse programming techniques for voltage-controlled magnetoresistive tunnel junction (MTJ)
#114Magnetization controlling element using magnetoelectric effect
#115Memory devices with improved refreshing operations
#116Write pulse width scheme in a resistive memory
#117Method and apparatus for increasing the reliability of an access transitor coupled to a magnetic tunnel junction (MTJ)
#118Advanced programming verification schemes for analog memory cells
#119Methods and devices for healing reset errors in a magnetic memory
#120Semiconductor storage device
#121PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ)
#122MRAM smart bit write algorithm with error correction parity bits
#123Magnetic random access memory apparatus, methods for programming and verifying reference cells therefor
#124Method of operating a nonvolatile memory by reprogramming failed cells using a reinforced program pulse in an idle state and memory system thereof
#125CONFIGURABLE MEMORY ARRAY
#126Resistive memory and related method of operation
#127Stabilization of resistive memory
#128Method and apparatus for increasing the reliability of an access transitor coupled to a magnetic tunnel junction (MTJ)
#129Semiconductor storage device
#130Method and apparatus for writing to a magnetic tunnel junction (MTJ) by applying incrementally increasing voltage level
#131Non-volatile memory array configurable for high performance and high density
#132Method and apparatus pertaining to a ferroelectric random access memory
#133Method and apparatus pertaining to a ferroelectric random access memory
#134STORAGE DEVICE AND WRITING CONTROL METHOD
#135Magnetic random access memory apparatus, methods for programming and verifying reference cells therefor
#136Non-volatile memory device and method for programming the same
#137Magnetic Memory Cell With Multi-Level Cell (MLC) Data Storage Capability
#138Memory write error correction circuit
#139MRAM cells and circuit for programming the same
#140Method and apparatus for programming a magnetic tunnel junction (MTJ)
#141Spin memory and spin transistor
#142Non-volatile memory cell with precessional switching
#143Nonvolatile memory device
#144Magnetic memory
#145Stuck-at defect condition repair for a non-volatile memory cell
#146Method and apparatus for increasing the reliability of an access transitor coupled to a magnetic tunnel junction (MTJ)
#147Stuck-at defect condition repair for a non-volatile memory cell
#148Non-volatile memory read/write verify
#149Programming MRAM cells using probability write
#150Non-volatile memory cell with precessional switching
#151SEMICONDUCTOR DEVICE
#152Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance
#153Data storage devices using magnetic domain wall movement and methods of operating the same
#154Magnetic random access memory and operation method thereof
#155Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance
#156Apparatus and method for memory operations using address-dependent conditions
#1571R1D MRAM block architecture
#158Magnetic storage apparatus using ferromagnetic tunnel junction device
#159Dual data protection in storage devices
#160Magnetic memory and method of writing data
#161Dynamic control of spin states in interacting magnetic elements
#162Method of sensing data in magnetic random access memory with overlap of high and low resistance distributions