199465 ⎘
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements; Auxiliary circuits Address circuits or decoders
Sub-classes:SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF
#2IMPRINT RECOVERY MANAGEMENT FOR MEMORY SYSTEMS
#3THREE-DIMENSIONAL MEMORY DEVICES
#4Techniques to manufacture ferroelectric memory devices
#5Thin film transistor deck selection in a memory device
#6Non-volatile memory devices and systems with volatile memory features and methods for operating the same
#7Content addressable memory device and operating method thereof
#8Wordline capacitance balancing
#9Thin film transistor deck selection in a memory device
#10Thin film transistor deck selection in a memory device
#11Three-dimensional memory device
#12Circuit partitioning for a memory device
#13Method for manufacturing a three-dimensional memory
#14Wordline capacitance balancing
#15Non-volatile memory devices and systems with volatile memory features and methods for operating the same
#16Multiple concurrent modulation schemes in a memory system
#17Wear leveling for random access and ferroelectric memory
#18Speculative section selection within a memory device
#19Full bias sensing in a memory array
#20Sense amplifier with lower offset and increased speed
#21Non-volatile memory devices and systems with read-only memory features and methods for operating the same
#22Imprint recovery management for memory systems
#23Wordline capacitance balancing
#24Circuit partitioning for a memory device
#25Speculative section selection within a memory device
#26Charge sharing between memory cell plates
#27Data caching for ferroelectric memory
#28Memory cell driver, memory cell arrangement, and methods thereof
#29Ferroelectric memory cells
#30Offset cancellation for latching in a memory device
#31Wear leveling
#32Periphery fill and localized capacitance
#33Variable filter capacitance
#34Sense amplifier with lower offset and increased speed
#35Multiple concurrent modulation schemes in a memory system
#36Charge sharing between memory cell plates
#37Apparatuses and methods for shielded memory architecture
#38Wear leveling for random access and ferroelectric memory
#39Non-volatile memory devices and systems with read-only memory features and methods for operating the same
#40Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory
#41Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
#42Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
#43Wear leveling
#44Non-volatile memory devices and systems with read-only memory features and methods for operating the same
#45Non-volatile memory devices and systems with volatile memory features and methods for operating the same
#46Sense amplifier with lower offset and increased speed
#47Ferroelectric memory cells
#48Ferroelectric memory cell recovery
#49Power reduction for a sensing operation of a memory cell
#50Periphery fill and localized capacitance
#51Offset cancellation for latching in a memory device
#52Writing to cross-point non-volatile memory
#53Mitigating line-to-line capacitive coupling in a memory die
#54Charge sharing between memory cell plates using a conductive path
#55Multiple concurrent modulation schemes in a memory system
#56Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
#57Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
#58Ferroelectric memory expansion for firmware updates
#59Ferroelectric memory cell recovery
#60Apparatuses and methods for shielded memory architecture
#61Wear leveling for random access and ferroelectric memory
#62Memory device
#63Wear leveling
#64Variable filter capacitance
#65Ferroelectric memory cells
#66Data caching for ferroelectric memory
#67Bias control circuit with distributed architecture for memory cells
#68Full bias sensing in a memory array
#69Power reduction for a sensing operation of a memory cell
#70Resistance change type memory
#71Ferroelectric memory cell recovery
#72Writing to cross-point non-volatile memory
#73Full bias sensing in a memory array
#74Ferroelectric memory cells
#75Writing to cross-point non-volatile memory
#76Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
#77Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
#78Ferroelectric memory cell recovery
#79Charge sharing between memory cell plates using a conductive path
#80Access methods of memory device using relative addressing
#81Ferroelectric memory expansion for firmware updates
#82Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
#83Semiconductor memory device including switches for selectively turning on bit lines
#84Nonvolatile semiconductor storage device having improved reading and writing speed characteristics
#85Ferroelectric memory with shunt device
#86Ferroelectric memory apparatus and control method of the same
#87Thin film transistor deck selection in a memory device
#88Periphery fill and localized capacitance
#89Offset cancellation for latching in a memory device
#90Writing to cross-point non-volatile memory
#91Ferroelectric memory cell recovery
#92Hybrid reference generation for ferroelectric random access memory