199471 ⎘
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements; Auxiliary circuits Verifying circuits or methods
DISTURBANCE-RESILIENT MEMORY ARCHITECTURE WITH INDEPENDENT PASS CONTROL FOR NON-VOLATILE TRANSISTOR ARRAYS
#2METHODS FOR ACTIVITY-BASED MEMORY MAINTENANCE OPERATIONS AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
#3FERROELECTRIC TRANSISTOR AND METHOD OF OPERATING THE SAME
#4OPERATION METHOD OF FERROELECTRIC MEMORY
#5NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF
#6METHODS FOR ACTIVITY-BASED MEMORY MAINTENANCE OPERATIONS AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
#7Data processing method, data processing circuit, and computing apparatus
#8Methods for activity-based memory maintenance operations and memory devices and systems employing the same
#9Integrated assemblies having ferroelectric transistors and methods of forming integrated assemblies
#10Memory system configured to perform a reset on one or more non-volatile memory cells upon transitioning power states
#11Memory device and method having a control circuit configured to acquire information on a state of a control target, causes the control target to execute a read and write operation based on the state
#12Memory device
#13Semiconductor memory device
#14Semiconductor storage device
#15Ferroelectric random-access memory with ROMFUSE area having redundant configuration wordlines
#16Tunable resistive element
#17Method for testing a memory device
#18Methods for activity-based memory maintenance operations and memory devices and systems employing the same
#19Selector threshold compensation
#20Semiconductor storage device
#21Dual mode memory array security apparatus, systems and methods
#22Compensating for variations in selector threshold voltages
#23Optimal write method for a ferroelectric memory
#24Non-volatile ferroelectric memory cells with multilevel operation
#25Dynamic enabling of redundant memory cells during operating life
#26Dual mode memory array security apparatus, systems and methods
#27Ferroelectric memory expansion for firmware updates
#28Ferroelectric memory write-back
#29Ferroelectric random access memory with single plate line pulse during read
#30Memory device, memory cell arrangement, and methods thereof