System, apparatus, and method to increase read and write stability of scaled SRAM memory cells

Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation

RAM macro and timing generating circuit thereof

SRAM having active write assist for improved operational margins

Semiconductor memory device and its test method

Method for implementing SRAM cell write performance evaluation

Test device, SRAM test device, semiconductor integrated circuit device and methods of fabricating the same

METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS MEMORY CELL FOR IMPROVED PERFORMANCE

Speedpath repair in an integrated circuit

Memory device and testing with write completion detection

Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO)

Dynamic voltage adjustment for memory

Shift register latch with embedded dynamic random access memory scan only cell

Controlling memory devices that have on-die termination

Programmable pulsewidth and delay generating circuit for integrated circuits

METHOD AND STRUCTURE FOR DOMINO READ BIT LINE AND SET RESET LATCH

Semiconductor integrated circuit capable of testing with small scale circuit configuration

System for bitcell and column testing in SRAM

Storage cell design evaluation circuit including a wordline timing and cell access detection circuit

Test system and failure parsing method thereof

Efficient memory product for test and soft repair of SRAM with redundancy

Method and apparatus for measuring device mismatches

Semiconductor integrated circuit

Generalized interlocked register cell (GICE)

Test circuit arrangement

Memory device with reduced standby power consumption and method for operating same

Device threshold calibration through state dependent burn-in

SEMICONDUCTOR INTEGRATED CIRCUIT

Structure for integrated circuit for measuring set-up and hold times for a latch element

Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages

Testing for SRAM memory data retention

Method of testing semiconductor apparatus

Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array

Defect analysis methods for semiconductor integrated circuit devices and defect analysis systems

Scanning Latches Using Selecting Array

Memory cell bit valve loss detection and restoration

BIST CIRCUIT DEVICE AND SELF TEST METHOD THEREOF

Application level testing of instruction caches in multi-processor/multi-core systems

Byte writeable memory with bit-column voltage selection and column redundancy

Scanning Latches Using Selecting Array

Method for evaluating storage cell design using a wordline timing and cell access detection circuit

Method for evaluating memory cell performance

Multiple-port SRAM device

Semiconductor memory device having the operating voltage of the memory cell controlled

Memory device with configurable delay tracking

Semiconductor integrated circuit

Memory write timing system

Memory diagnosis test circuit and test method using the same

Parallel bit test circuit and method

SRAM static noise margin test structure suitable for on chip parametric measurements

Method for powering an electronic device and circuit

Semiconductor integrated circuit and BIST circuit design method

Self-timing circuit with programmable delay and programmable accelerator circuits

Sense-amplifier assist (SAA) with power-reduction technique

Circuit and method to measure threshold voltage distributions in SRAM devices

Synchronous global controller for enhanced pipelining

Method to identify or screen VMIN drift on memory cells during burn-in or operation

Method and circuit arrangement for operating a volatile random access memory as a detector

Method and apparatus for measuring device mismatches

Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability

SENSE-AMPLIFIER ASSIST (SAA) WITH POWER-REDUCTION TECHNIQUE

Apparatus and method for interfacing to a memory

Integrated circuit with graduated on-die termination

Semiconductor memory device and semiconductor device

Yield calculation method

Methods and apparatus for inline characterization of high speed operating margins of a storage element

Apparatus and methods for determining memory device faults

Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance

Semiconductor integrated circuit and the same checking method

Method of operating a memory system

Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same

Internally asymmetric method for evaluating static memory cell dynamic stability

Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same

Method for evaluating leakage effects on static memory cell access time

Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit

Methods and apparatus for random number generation

Static random access memory (SRAM) with clamped source potential in standby mode

Semiconductor memory device

Method for testing transistors having an active region that is common with other transistors and a testing circuit for accomplishing the same

Block redundancy implementation in heirarchical ram's

Method for SRAM bitmap verification

Semiconductor memory device and its test method

Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability

Bitline variable methods and circuits for evaluating static memory cell dynamic stability

Flood mode implementation for continuous bitline local evaluation circuit

Semiconductor memory device having read operation testing function

Method and circuit for reducing degradation in a regulated circuit

Built-in self-test method and system

Device and method for configuring a cache tag in accordance with burst length

Method for analyzing defect of SRAM cell

Non-volatile memory cell integrated with a latch

Method for determining and classifying SRAM bit fail modes suitable for production test implementation and real time feedback

Mechanism for implementing redundancy to mask failing SRAM

Semiconductor memory device and semiconductor device

Analytic structure for failure analysis of semiconductor device

High density SRAM cell with latched vertical transistors

Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same

Method for self-correcting cache using line delete, data logging, and fuse repair correction

Processes for turning a SRAM cell off and processess for writing a SRAM cell

Method for reducing SRAM test time by applying power-up state knowledge

Test for weak SRAM cells

Efficient method of test and soft repair of SRAM with redundancy

ABIST data compression and serialization for memory built-in self test of SRAM with redundancy

Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy

Multifunctional latch circuit for use with both SRAM array and self test device

Local bit select circuit with slow read recovery scheme

Semiconductor memory device

System and method for calibrating weak write test mode (WWTM)

Integrated circuit device having a test circuit to measure AC characteristics of internal memory macro

Stacked memory cell utilizing negative differential resistance devices

Static random access memory and pseudo-static noise margin measuring method

Flood mode implementation for continuous bitline local evaluation circuit

Memory circuit with redundant memory cell array allowing simplified shipment tests and reduced power consumptions

Circuit for verifying the write speed of SRAM cells

Design techniques to increase testing efficiency

Semiconductor memory device having the operating voltage of the memory cell controlled

Scanning latches using selecting array

High reliability triple redundant latch with integrated testability

Computer systems

Method and apparatus for high speed testing of latch based random access memory

Synchronous global controller for enhanced pipelining

Cache late select circuit

Output driver with pulse to static converter

Device and method for configuring a cache tag in accordance with burst length

Ternary bit line signaling

Memory cell testing feature

Method and circuit for locating anomalous memory cells

Flip-flop circuit having majority-logic circuit

Semiconductor integrated circuit and method for detecting soft defects in static memory cell

Efficent column redundancy techniques

Semiconductor memory device having the operating voltage of the memory cell controlled

Method and apparatus for test and repair of marginally functional SRAM cells

Synchronous controlled, self-timed local SRAM block

SRAM device and a method of operating the same to reduce leakage current during a sleep mode

Burn in system and method for improved memory reliability

Method and apparatus for characterizing shared contacts in high-density SRAM cell design

Semiconductor integrated circuit including semiconductor memory

Method for analyzing defect of SRAM cell

Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell

Method of testing an integrated circuit and an integrated circuit test apparatus

Test key for bridge and continuity testing

Memory bit line leakage repair

Semiconductor memory device providing redundancy

Circuits and methods for characterizing random variations in device characteristics in semiconductor integrated circuits

Semiconductor memory including error correction function

System and method for self-adaptive redundancy choice logic

Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device

Stacked FET SRAM design

Ultra-low supply-voltage static random-access memory (SRAM) with 8-transistor cell with P and N pass gates to same bit lines

Memory device latch circuitry

Counter design with various widths for image sensor

Post-packaging repair of redundant rows

Self-gating pulsed flip-flop

Method for combining NVM class and SRAM class MRAM elements on the same chip

Method of and circuit for generating a physically unclonable function

Memory cell with de-initialization circuitry

Wordline under-driving using a virtual power network

Method and apparatus for memory speed characterization

Systems and methods for avoiding read disturbance in a static random-access memory (SRAM)

High reliability non-volatile static random access memory devices, methods and systems

Two gate pitch FPGA memory cell