199505 ⎘
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
Sub-classes:Scannable SRAM
#2DISPLAY DEVICE
#3SYSTEM FOR IDENTIFYING POINTS OF COMPROMISE
#4Static Random Access Memory
#5DISPLAY DEVICE
#6System for identifying points of compromise
#7Display device
#8Inverter including transistors having different threshold voltages and memory cell including the same
#9Display device
#10Systems And Methods For Generating A Temperature Dependent Supply Voltage
#11METHOD FOR MANUFACTURING SRAM MEMORY CIRCUIT
#12Memory device with real-time monitoring
#13INTEGRATED CIRCUIT THAT APPLIES DIFFERENT DATA INTERFACE TERMINATIONS DURING AND AFTER WRITE DATA RECEPTION
#14Event-based extraction of features in a convolutional spiking neural network
#15Event-based classification of features in a reconfigurable and temporally coded convolutional spiking neural network
#16Display device
#17Acceleration of data queries in memory
#18Test circuit for testing a storage circuit
#19Static random access memory
#20Switched artificial synapse
#21System for identifying points of compromise
#22Voltage and temperature adaptive memory leakage reduction bias circuit
#23Memory device latch circuitry
#24Display device
#25SRAM structure and method for manufacturing SRAM structure
#26Memory circuit and manufacturing method thereof
#27Event-based classification of features in a reconfigurable and temporally coded convolutional spiking neural network
#28Integrated circuit that applies different data interface terminations during and after write data reception
#29On-die termination control
#30Static random access memory method
#31Test system
#32Control system, control method and nonvolatile computer readable medium for operating the same
#33Sense amplifier based flip-flop capable of resolving metastable state by removing unintentional current from output nodes
#34Testing circuit, testing method, and apparatus for testing multi-port random access memory
#35Display device
#36SRAM structure and method for manufacturing SRAM structure
#37Transaction-based on-die termination
#38Post-packaging repair of redundant rows
#39Multi-resistance MRAM
#40Components including structures having decoupled load paths
#41Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows
#42Fault detection circuitry
#43Multi-resistance MRAM
#44System to compare at least one DNA fragment to a reference genome
#45Magnetic memory chip having nvm class and SRAM class MRAM elements on the same chip
#46Semiconductor device and semiconductor apparatus
#47Capacitive-based determination of micromirror status
#48Display device
#49Static random access memory circuit
#50Integrated circuit copy prevention device powered by a photoelectric cell
#51Flip-flop with single pre-charge node
#52Memory component with on-die termination
#53Semiconductor circuit, method of driving semiconductor circuit, and electronic apparatus
#54FinFET-based memory testing using multiple read operations
#55Semiconductor device
#56Fuse array and memory device
#57SRAM-based authentication circuit
#58Logic devices, digital filters and video codecs including logic devices, and methods of controlling logic devices
#59FinFET-based memory testing using multiple read operations
#60Semiconductor device, electronic device, and driving method thereof
#61Array power supply-based screening of static random access memory cells for bias temperature instability
#62Data processing method and apparatus
#63On-die termination control
#64Semiconductor structure and memory device including the structure
#65Static random access memory circuits
#66Transistor gain cell with feedback
#67Energetic potting materials, electronic devices potted with the energetic potting materials, and related methods
#68Display device
#69Error counters on a memory device
#70Method and apparatus for generating featured test pattern
#71Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells
#72On-die termination control
#73Reconfigurable semiconductor integrated circuit and electronic device
#74Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication
#75Semiconductor system and device
#76Method and apparatus for testing memory
#77Two-transistor SRAM semiconductor structure and methods of fabrication
#78Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication
#79Design-for-test apparatuses and techniques
#80Semiconductor memory device
#81Memory architecture with local and global control circuitry
#82Controlling a flash device having time-multiplexed, on-die-terminated signaling interface
#83Static ram
#84Memory chip and layout design for manufacturing same
#85Array power supply-based screening of static random access memory cells for bias temperature instability
#86Error injection and error counting during memory scrubbing operations
#87Apparatus and method for preventing error in physically unclonable function
#88Array power supply-based screening of static random access memory cells for bias temperature instability
#89Array power supply-based screening of static random access memory cells for bias temperature instability
#90Assist circuits for SRAM testing
#918T based SRAM cell and related method
#92Semiconductor device including stacked circuits
#93Error injection and error counting during memory scrubbing operations
#94Memory array
#95Memory unit and method of testing the same
#96Semiconductor structure and memory device including the structure
#97Controlling on-die termination in a nonvolatile memory
#98Memory device with programmed device address and on-die-termination
#99Nonvolatile memory with command-driven on-die termination
#100Nonvolatile memory with chip-select/device-address triggered on-die termination
#101Nonvolatile memory device with on-die control and data signal termination
#102Configuration bit architecture for programmable integrated circuit device
#103Memory devices and control methods thereof
#104Circuit and data processor with headroom monitoring and method therefor
#105Semiconductor device
#106Detecting and correcting hard errors in a memory array
#107Method of measuring threshold voltage of MOS transistor in SRAM array
#108Semiconductor device
#109Three dimensional cross-access dual-port bit cell design
#110Dynamic static random access memory (SRAM) array characterization using an isolated bit-line
#111Buffered memory module having multi-valued on-die termination
#112Semiconductor integrated circuit device
#113Method of detecting transistors mismatch in a SRAM cell
#114Sense amplifier with transistor threshold compensation
#115Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability
#116PHASE SWITCHABLE BISTABLE MEMORY DEVICE, A FREQUENCY DIVIDER AND A RADIO FREQUENCY TRANSCEIVER
#117Circuit for reverse biasing inverters for reducing the power consumption of an SRAM memory
#118Memory circuit
#119Metal-insulator phase transition flip-flop
#120Circuit arrangement, a method for testing a supply voltage provided to a test circuit, and a method for repairing a voltage source
#121Semiconductor memory device including flag cells
#122Ground-referenced single-ended memory interconnect
#123Memory with bit line current injection
#124Timing logic for memory array
#125Process corner sensor for bit-cells
#126pBIST engine with reduced SRAM testing bus width
#127Storage circuit
#128Logic devices, digital filters and video codecs including logic devices, and methods of controlling logic devices
#129Testing of SRAMS
#130Memory architecture with local and global control circuitry
#131SRAM with buffered-read bit cells and its testing
#132Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell
#133Testing signal development on a bit line in an SRAM
#134Initializing dummy bits of an SRAM tracking circuit
#135Multiple-port SRAM device
#136Time processing method and circuit for synchronous SRAM
#137Testing retention mode of an SRAM array
#138Semiconductor memory device and method of testing the same
#139Semiconductor device including negative bias voltage generation circuit
#140Fault-aware mapping for shared last level cache (LLC)
#141Test circuit for testing refresh circuitry of a semiconductor memory device
#142Ring oscillator and semiconductor device
#143Memory device having control circuitry for write tracking using feedback-based controller
#144Semiconductor integrated circuit device
#145Threshold voltage measurement device
#146Memory cell having flexible read/write assist and method of using
#147Memory devices and control methods thereof
#148Integrated circuit with stress generator for stressing test devices
#149Weak bit detection in a memory through variable development time
#150Method and apparatus for testing a memory device
#151Temperature-profiled device fingerprint generation and authentication from power-up states of static cells
#152Memory cell and memory array
#153Repair device and method for integrated circuit structured arrays
#154Memory with bit line current injection
#155Fault Tolerant Static Random-Access Memory
#156Memory with variable strength sense amplifier
#157Memory with bit line capacitive loading
#158Secure non-volatile memory
#159SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor
#160Oscillato based on a 6T SRAM for measuring the bias temperature instability
#161Static noise margin monitoring circuit and method
#162Tracking capacitive loads
#163Memory circuit and method for routing the memory circuit
#164Functional screening of static random access memories using an array bias voltage
#165Quantifying the read and write margins of memory bit cells
#166SRAM timing tracking circuit
#167Using a precharge characteristics of a node to validate a previous data/signal value represented by a discharge of said node
#168SEMICONDUCTOR MEMORY DEVICE
#169SRAM memory device and testing method thereof
#170Method for detecting permanent faults of an address decoder of an electronic memory device
#171Fast parallel test of SRAM arrays
#172Static random access memory test structure
#173Method of screening static random access memory cells for positive bias temperature instability
#174Code-based differential charging of bit lines of a sense amplifier
#175Semiconductor memory device capable of screening a weak bit and repairing the same
#176Method of screening static random access memories for pass transistor defects
#177Memory device and systems including the same
#178Method of stressing static random access memories for pass transistor defects
#179Device and method for detecting resistive defect
#180Method of screening static random access memories for unstable memory cells
#181Array power supply-based screening of static random access memory cells for bias temperature instability
#182Semiconductor system and device
#183Methods for testing a memory embedded in an integrated circuit
#184Detecting random telegraph noise induced failures in an electronic memory
#185Semiconductor memory device and test method therefor
#186Low power retention random access memory with error correction on wake-up
#187Complementary SOI lateral bipolar for SRAM in a low-voltage CMOS platform
#188Test system which shares a register in different modes
#189SRAM write assist apparatus
#190Controlling on-die termination in a dynamic random access memory device
#191Memory element and signal processing circuit
#192Temperature-profiled device fingerprint generation and authentication from power-up states of static cells
#193Static random access memory (SRAM) and test method of the SRAM having precharge circuit to prepcharge bit line
#194Memory circuit
#195Synchronous global controller for enhanced pipelining
#196Circuits and Methods for Characterizing Random Variations in Device Characteristics in Semiconductor Integrated Circuits
#197Improving read stability of a semiconductor memory
#19810T SRAM cell with near dual port functionality
#199Static RAM
#200Secure storage of a codeword within an integrated circuit
#201Secure non-volatile memory
#202DIAGNOSTIC CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
#203Semiconductor integrated circuit having a test function for detecting a defective cell
#204Adaptive and dynamic stability enhancement for memories
#205Key extraction in an integrated circuit
#206Latch based memory device
#207Multiple bitcells tracking scheme for semiconductor memories
#208SEMICONDUCTOR MEMORY DEVICE
#209SRAM with buffered-read bit cells and its testing
#210Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through Capability
#211Memory testing system
#212Margin testing of static random access memory cells
#213TESTING MEMORY ARRAYS AND LOGIC WITH ABIST CIRCUITRY
#214Controlling dynamic selection of on-die termination
#215Test device and semiconductor integrated circuit device
#216Dynamic on-die termination selection
#217Memory repair
#218Semiconductor nanowire memory device
#219Method and apparatus for testing a memory device
#220Method for detecting and correcting errors for a memory whose structure shows dissymmetrical behavior, corresponding memory and its use
#22110T SRAM cell with near dual port functionality
#222Information storage device and test method of setting a test condition for information storage device outside range of presupposed real use conditions
#223Integrated solution for identifying malfunctioning components within memory devices
#224Integrated circuit device with dynamically selected on-die termination
#225Voltage regulation circuitry
#226SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM AND ELECTRONIC EQUIPMENT
#227Closed-loop soft error rate sensitivity control
#228SRAM macro test flop
#229Semiconductor integrated circuit
#230Method and structure for SRAM cell trip voltage measurement
#231Method and structure for SRAM Vmin/Vmax measurement
#23210T SRAM cell with near dual port functionality
#233Semiconductor memory device
#234Memory circuits, systems, and methods for routing the memory circuits
#235Semiconductor memory device
#236Structure and method for screening SRAMS
#237Static noise margin estimation
#238Mechanism for measuring read current variability of SRAM cells
#239Integrated circuit with a memory matrix with a delay monitoring column
#240Memory controller that controls termination in a memory device
#241SEMICONDUCTOR MEMORY DEVICE
#242Multiple-port SRAM device
#243System for bitcell and column testing in SRAM
#244Integrated circuit memory having assisted access and method therefor
#245Integrated circuit having an embedded memory and method for testing the memory
#246Method for constructing Shmoo plots for SRAMs
#247SRAM and testing method of SRAM
#248Integrated circuit memory power supply
#249Semiconductor memory device and test method therefor
#250Burn-in methods for static random access memories and chips
#251Detecting asymmetrical transistor leakage defects
#252SEMICONDUCTOR MEMORY DEVICE AND SELF-TEST METHOD OF THE SAME
#253Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels
#254Synchronous global controller for enhanced pipelining
#255Semiconductor memory device and methods of performing a stress test on the semiconductor memory device
#256Double data rate converter circuit includes a delay locked loop for providing the plurality of clock phase signals
#257Method for evaluating SRAM memory cell and computer readable recording medium which records evaluation program of SRAM memory cell
#258Bitline leakage detection in memories
#259Semiconductor memory device
#260Memory repair
#261Memory having self-timed bit line boost circuit and method therefor
#262Semiconductor device and method for designing the same
#263Circuit and method for optimizing memory sense amplifier timing
#264Static random access memory (SRAM) and test method of the SRAM having precharge circuit to precharge bit line
#265Semiconductor memory device and trimming method thereof
#266Functional float mode screen to test for leakage defects on SRAM bitlines
#267Method for testing a static random access memory
#268Test device and semiconductor integrated circuit device
#269Test device and semiconductor integrated circuit device
#270Column selectable self-biasing virtual voltages for SRAM write assist
#271Temperature-profiled device fingerprint generation and authentication from power-up states of static cells
#272High performance read bypass test for SRAM circuits
#273Block redundancy implementation in hierarchical rams
#274Methods for characterizing device variation in electronic memory circuits
#275Programmable pulsewidth and delay generating circuit for integrated circuits
#276Method and apparatus for testing a random access memory device
#277Testing a memory device having field effect transistors subject to threshold voltage shifts caused by bias temperature instability
#278Memory-module buffer with on-die termination
#279High-speed testing of integrated devices
#280Semiconductor memory device
#281CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM ARRAYS
#282Data processing apparatus and method for testing stability of memory cells in a memory device
#283Characterization of bits in a functional memory
#284Apparatus for testing memory device
#285Static random access memory having cells with junction field effect and bipolar junction transistors
#286MULTIPLE-PORT SRAM DEVICE
#287Test apparatus for determining if adjacent contacts are short-circuited and semiconductor integrated circuit devices that include such test apparatus
#288Memory including a performance test circuit
#289Design Structure for a Circuit and Method to Measure Threshold Voltage Distributions in SRAM Devices
#290Method and system for determining element voltage selection control values for a storage device
#291On-chip characterization of noise-margins for memory arrays
#292Method and apparatus for screening bit line of a static random access memory (SRAM) for excessive leakage current
#293Apparatus for implementing SRAM cell write performance evaluation
#294Single via structured IC device
#295Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator
#296Method and apparatus for SRAM macro sparing in computer chips
#297Integrated circuit memory having dynamically adjustable read margin and method therefor
#298Device Threshold Calibration Through State Dependent Burnin
#299Circuits and methods for characterizing device variation in electronic memory circuits
#300Semiconductor Memory Device