ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

HIERARCHICAL MEMORY ARCHITECTURE INCLUDING ON-CHIP MULTI-BANK NON-VOLATILE MEMORY WITH LOW LEAKAGE AND LOW LATENCY

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

SRAM WITH PUF DEDICATED SECTOR STANDING-BY

Reusing memory arrays for physically unclonable function (PUF) generation

SRAM power switching with reduced leakage, noise rejection, and supply fault tolerance

Keeper-free volatile memory system

Semiconductor chip, method of fabricating thereof, and method of testing a plurality of semiconductor chips

ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

Selectively cross-coupled inverters, and related devices, systems, and methods

Hardware accelerator with analog-content addressable memory (a-CAM) for decision tree computation

Dual compare ternary content addressable memory

Environmental sensor or semiconductor device

Apparatus and method and computer program product for verifying memory interface

SRAM with error correction in retention mode

Static random-access memory with capacitor which has finger-shaped protrudent portions and related fabrication method

Method for controlling power supply in semiconductor device

Semiconductor device and data retention method

X-ray detector, semiconductor memory device including the same, method of testing semiconductor memory device and method of manufacturing semiconductor memory device

Semiconductor memory apparatus

Clocked miller latch design for improved soft error rate

Complementary dual-modular redundancy memory cell

SRAM with error correction in retention mode

Semiconductor device

Hybrid configuration memory cell

Lower-power semiconductor memory device

Semiconductor circuit, driving method, and electronic apparatus

Environmental sensor or semiconductor device

SRAM with error correction in retention mode

Memory elements with soft-error-upset (SEU) immunity using parasitic components

Storage bitcell

Memory with single-event latchup prevention circuitry

Memory cell of static random access memory based on DICE structure

Non-volatile SRAM cell using resistive memory elements

Retention minimum voltage determination techniques

Memory cell of static random access memory based on resistance and capacitance hardening

Static random access memory unit cell

Semiconductor device

Retention voltage generation circuit and electronic apparatus

Semiconductor memory with data line capacitive coupling

Storage device, method for operating storage device, semiconductor device, electronic component, and electronic device

Semiconductor device

Autonomous device for detecting characteristics of a medium to be measured and method therefor

Memory cell of static random access memory based on resistance hardening

Dual-port SRAM connection structure

Semiconductor structure and memory device including the structure

Static random access memory device with vertical FET devices

Semiconductor memory with data line capacitive coupling

Integrated structure comprising neighboring transistors

Method and apparatus for identifying erroneous data in at least one memory element

Digital test system

Word line driver comprising NAND circuit

Semiconductor memory with data line capacitive coupling

Semiconductor device

Cell structure of 4T random access memory, random access memory and operation methods

Low power radiation hardened memory cell

Semiconductor device including first and second MISFETs

Transistors with source and word line voltage adjusting circuitry for controlling leakage currents and its method thereof

Low-power semiconductor device

Latch circuit and semiconductor device including the same

Radiation upset detection

Dual-port SRAM connection structure

Integrated structure comprising neighboring transistors

Semiconductor structure and memory device including the structure

Configuration bit architecture for programmable integrated circuit device

Static memory cell

Passive SRAM write assist

Semiconductor memory with data line capacitive coupling

Circuit having capacitor coupled with memory element

Digital test system

Eight transistor soft error robust storage cell

Memory array with redundant bits and memory element voting circuits

Semiconductor device with logic circuit, SRAM circuit and standby state

Low power static random access memory

Memory cell array latchup prevention

SRAM voltage assist

Method and apparatus for measuring alpha particle induced soft errors in semiconductor devices

Memory using voltage to improve reliability for certain data types

Memory elements with stacked pull-up devices

Integrated circuit having improved radiation immunity

Weak power supply operation and control

Semiconductor device and driving method thereof

Integrated circuit having improved radiation immunity

Five transistor SRAM cell

SRAM bitcell implemented in double gate technology

Integrated circuit with automatic deactivation upon exceeding a specific ion linear energy transfer (LET) value

Nonvolatile memory apparatus

Register protected against fault attacks

Memory device correcting the effect of collision of high-energy particles

Memory element and signal processing circuit

Method and apparatus for controlling state information retention in an apparatus

METHOD AND APPARATUS FOR DIRECT BACKUP OF MEMORY CIRCUITS

Memory cell supply voltage control based on error detection

Semiconductor device and method of manufacturing the same

Semiconductor device

Storage circuitry and method with increased resilience to single event upsets

Volatile memory elements with soft error upset immunity

Measurement device and measurement method

Semiconductor memory device

Memory array with redundant bits and memory element voting circuits

SRAM cell

Single event upset hardened static random access memory cell

Stable SRAM bitcell design utilizing independent gate FinFET

Memory cell supply voltage control based on error detection

Memory elements with soft error upset immunity

Semiconductor device

Method for detecting and correcting errors for a memory whose structure shows dissymmetrical behavior, corresponding memory and its use

Semiconductor integrated circuit including a logic circuit module with a plurality of photodetectors

Structure and method for improving storage latch susceptibility to single event upsets

Semiconductor integrated circuit device and process for manufacturing the same

Semiconductor device

Semiconductor integrated circuit device and process for manufacturing the same

Closed-loop soft error rate sensitivity control

Semiconductor integrated circuit device and process for manufacturing the same

Single-event upset immune static random access memory cell circuit

METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVCIE HAVING CAPACITOR ELEMENT

METHOD OF DETECTING A LIGHT ATTACK AGAINST A MEMORY DEVICE AND MEMORY DEVICE EMPLOYING A METHOD OF DETECTING A LIGHT ATTACK

Semiconductor memory device

Semiconductor memory and program

Volatile memory elements with soft error upset immunity

Providing capacitors to improve radiation hardening in memory elements

Soft error robust storage SRAM cells and flip-flops

Volatile memory elements with soft error upset immunity

Volatile memory elements with soft error upset immunity

Heavy Ion Upset Hardened Floating Body SRAM Cells

Eight transistor soft error robust storage cell

Semiconductor integrated circuit

Methods and systems to write to soft error upset tolerant latches

Semiconductor device

Volatile memory elements with soft error upset immunity

Non-volatile single-event upset tolerant latch circuit

Semiconductor integrated circuit having latch circuit applied changeable capacitance and method thereof

Planar Metal-Insulator-Metal Circuit Element and Method for Planar Integration of Same

METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING CAPACITOR ELEMENT

Soft error robust static random access memory cell storage configuration.

Fault tolerant asynchronous circuits

Structure and method for improving storage latch susceptibility to single event upsets

SEMICONDUCTOR INTEGRATED CIRCUIT AND IC CARD SYSTEM

Apparatus and Method for Improving Storage Latch Susceptibility to Single Event Upsets

SRAM memory cell protected against current or voltage spikes

Semiconductor memory device

Soft error recoverable storage element and soft error protection technique

Apparatus and method for adjusting a supply voltage based on a read result

Semiconductor integrated circuit device

Radiation tolerant SRAM bit

Structure for a configurable SRAM system and method

Semiconductor integrated circuit device and process for manufacturing the same

SEU hardening circuit and method

Integrated circuit protected against short circuits and operating errors following the passage on an ionizing radiation

MONITORING IONIZING RADIATION IN SILICON-ON INSULATOR INTEGRATED CIRCUITS

Method of detecting a light attack against a memory device and memory device employing a method of detecting a light attack

Semiconductor device

Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region

CMOS storage devices configurable in high performance mode or radiation tolerant mode

Single-event upset immune static random access memory cell circuit, system, and method

Noise accommodating information storing apparatus

Memory unit

Deglitching circuits for a radiation-hardened static random access memory based programmable architecture

APPARATUS AND METHOD OF ERROR DETECTION AND CORRECTION IN A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY FIELD-PROGRAMMABLE GATE ARRAY

SRAM CIRCUITRY

Generalized interlocked register cell (GICE)

Static random access memory cell with improved stability

SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS FOR THE SAME

Apparatus for hardening a static random access memory cell from single event upsets

Soft error robust flip-flops

Radiation tolerant SRAM bit

High performance single event upset hardened SRAM cell

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME

SET HARDENED REGISTER

SRAM split write control for a delay element

Semiconductor integrated circuit device and process for manufacturing the same

Soft error robust static random access memory cells

Memory cell supply voltage control based on error detection

Semiconductor integrated circuit device and process for manufacturing the same

Method of manufacturing semiconductor integrated circuit device having capacitor element

Logic cell protected against random events

Semiconductor integrated circuit and IC card system having internal information protection

Cell structure with buried capacitor for soft error rate improvement

Semiconductor device

Data encoding approach for implementing robust non-volatile memories

Radiation-hardened programmable device

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

Semiconductor memory device and method of operating the semiconductor memory device

Method and apparatus for avoiding cell data destruction caused by SRAM cell instability

SRAM split write control for a delay element

Static noise-immune SRAM cells

Fault tolerant asynchronous circuits

Static random access memory cell with improved stability

Radiation-hardened memory element with multiple delay elements

Semiconductor integrated circuit device and process for manufacturing the same

SRAM with read assist

Real-time adaptive SRAM array for high SEU immunity

Semiconductor device

Logic SRAM cell with improved stability

Semiconductor integrated circuit with photo-detecting elements for reverse-engineering protection

Semiconductor integrated circuit and IC card system

SEU hardened latches and memory cells using programmable resistance devices

Radiation tolerant SRAM bit

Semiconductor storage device

Resistive cell structure for reducing soft error rate

SRAM circuitry

Radiation tolerant combinational logic cell

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

RAM cell with soft error protection using ferroelectric material

Dual redundant dynamic logic

Data holding circuit

SRAM, semiconductor memory device, method for maintaining data in SRAM, and electronic device

Semiconductor integrated circuit device and a method of manufacturing the same

Dual port semiconductor memory device

SRAM, semiconductor memory device, and method for maintaining data in SRAM

Lower minimum retention voltage storage elements

Semiconductor integrated circuit device and design method thereof

Semiconductor device

Method for connecting circuit elements within an integrated circuit for reducing single-event upsets

Proton and heavy ion SEU resistant SRAM

Semiconductor memory device

Single event effect (SEE) tolerant circuit design strategy for SOI type technology

Radiation-hardened SRAM cell with write error protection

Nonvolatile latch

Semiconductor integrated circuit device and process for manufacturing the same

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

Single-event upset tolerant static random access memory cell

Deglitching circuits for a radiation-hardened static random access memory based programmable architecture

Memory element with improved soft-error rate

Semiconductor device

SER immune cell structure

Semiconductor devices with reduced impact from alien particles

Redundancy register architecture for soft-error tolerance and methods of making the same

SRAM memory cell protected against current or voltage spikes

High reliability triple redundant memory element with integrated testability and voting structures on each latch

SRAM cell for soft-error rate reduction and cell stability improvement

SRAM circuitry

Resistive cell structure for reducing soft error rate

Method of manufacturing semiconductor integrated circuit device having capacitor element

Semiconductor device

Radiation-hardened programmable device

Radiation tolerant SRAM bit

Flip-flop circuit having majority-logic circuit

Data encoding approach for implementing robust non-volatile memories

Apparatus for increasing SRAM cell capacitance with metal fill

Negative differential resistance (NDR) memory device with reduced soft error rate

Semiconductor memory device

Method and apparatus for reducing soft errors

Redundant single event upset supression system

Semiconductor integrated circuit device and process for manufacturing the same

Dual-ported read SRAM cell with improved soft error immunity

Semiconductor integrated circuit device and process for manufacturing the same

Semiconductor integrated circuit device having capacitor element

Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array

Radiation hardened microelectronic device

Semiconductor integrated circuit device

Detector for alpha particle or cosmic ray

Circuit for and method of storing data in an integrated circuit device

Voltage regulator for generation of a voltage for a RAM cell

SRAM with error correction in retention mode

SRAM bitcell structures facilitating biasing of pull-up transistors

Redundancy schemes for memory cell repair

Redundancy schemes for memory

Memory cell with improved write margin

Layout of static random access memory array

Layout pattern for 8T-SRAM and the manufacturing method thereof

Configurable register circuitry for error detection and recovery