199756 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing; Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details Bit line control
Memory device bit line sensing system and method that compensates for bit line resistance variations
#302Programming rate identification and control in a solid state memory
#303METHOD AND STRUCTURE FOR DOMINO READ BIT LINE AND SET RESET LATCH
#304System for bitcell and column testing in SRAM
#305Method and apparatus for measuring device mismatches
#306Circuit and method for decoding column addresses in semiconductor memory apparatus
#307Flash memory device and writing method thereof
#308Circuit and method of testing a fail in a memory device
#309Method for evaluating memory cell performance
#310Method and system for in-situ parametric SRAM diagnosis
#311Built in self test transport controller architecture
#312Memory, integrated circuit and methods for adjusting a sense amp enable signal used therewith
#313Device and method including current measurement and/or amplification
#314Parallel bit test circuit and method
#315Method of detecting bit line bridge by selectively floating even-or odd-numbered bit lines of memory device
#316METHOD OF FIXING A READ EVALUATION TIME OR THE DIFFERENCE BETWEEN A READ CHARGE VOLTAGE AND A READ DISCRIMINATING VOLTAGE IN A NON-VOLATILE NAND TYPE MEMORY DEVICE
#317Phase change random access memory and method of testing the same
#318Method, apparatus and system relating to automatic cell threshold voltage measurement
#319Sense amplifier with leakage testing and read debug capability
#320Semiconductor memory and test method for the same
#321Method and apparatus for measuring device mismatches
#322Integrated Semiconductor Memory with a Test Function and Method for Testing an Integrated Semiconductor Memory
#323Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance
#324Hierarchical semiconductor memory device capable of carrying out a disturb refresh test on a memory array basis
#325Semiconductor memory
#326Electric fuse circuit providing margin read function
#327Semiconductor integrated circuit device
#328Semiconductor memory device having an open bit line structure, and method of testing the same
#329Semiconductor device generating a test voltage for a wafer burn-in test and method thereof
#330Semiconductor memory device and method of testing the same
#331Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate
#332Nonvolatile memory device having self reprogramming function
#333Semiconductor leakage current detector and leakage current measurement method, semiconductor leakage current detector with voltage trimming function and reference voltage trimming method, and semiconductor integrated circuit thereof
#334Semiconductor memory device
#335Semiconductor memory device comprising plural source lines
#336Ferroelectric memory to be tested by applying disturbance voltage to a plurality of ferroelectric capacitors at once in direction to weaken polarization, and method of testing the same
#337Memory core, memory device including a memory core, and method thereof testing a memory core
#338Method of reducing disturbs in non-volatile memory
#339Wafer-level burn-in test method, wafer-level burn-in test apparatus and semiconductor memory device
#340Semiconductor memory device and its test method
#341Bitline variable methods and circuits for evaluating static memory cell dynamic stability
#342METHOD FOR DETECTING A LEAKAGE CURRENT OF A SEMICONDUCTOR MEMORY
#343Semiconductor memory and burn-in test method of semiconductor memory
#344Semiconductor device and testing method thereof
#345Semiconductor memory device
#346Integrated circuit margin stress test system
#347Integrated semiconductor memory having sense amplifiers selectively activated at different timing
#348Full-stress testable memory device having an open bit line architecture and method of testing the same
#349Semiconductor memory device
#350Data path having grounded precharge operation and test compression capability
#351Integrated semiconductor memory device with adaptation of the evaluation characteristic of sense amplifiers
#352Integrated semiconductor memory device with test circuit for sense amplifier
#353Method and apparatus for current sense amplifier calibration in MRAM devices
#354Memory having internal column counter for compression test mode
#355Structure and method for measuring the channel boosting voltage of NAND flash memory at a node between drain/source select transistor and adjacent flash memory cell
#356DRAM memory with common pre-charger
#357Integrated semiconductor memory device including sense amplifiers
#358Direct memory access interface in integrated circuits
#359Memory device and test method thereof
#360Memory device having open bit line cell structure using burn-in testing scheme and method therefor
#361Artificial aging of chips with memories
#362Apparatus and method for testing semiconductor memory device
#363Method of reducing disturbs in non-volatile memory
#364Flash memory device capable of reducing test time and test method thereof
#365Refresh-free dynamic semiconductor memory device
#366Semiconductor memory with a data holding circuit having two output terminals
#367Data path having grounded precharge operation and test compression capability
#368Semiconductor memory device
#369Built-in self test circuit and test method for storage device
#370Method for testing an integrated semiconductor memory
#371Test method for a semiconductor memory
#372Non-volatile memory device and inspection method for non-volatile memory device
#373Semiconductor memory
#374Semiconductor memory
#375Method of reducing disturbs in non-volatile memory
#376Semiconductor integrated circuit and method for detecting soft defects in static memory cell
#377Semiconductor memory device, write control circuit and write control method for the same
#378Semiconductor integrated circuit including semiconductor memory
#379Method and apparatus for testing semiconductor memory device and related testing methods
#380Method and circuit for controlling generation of column selection line signal
#381Semiconductor memory device and method for testing same
#382Integrated memory and method for functional testing of the integrated memory
#383Circuit arrangement for setting a voltage supply for a test mode of an integrated memory
#384Method and circuit for precise timing of signals in an embedded DRAM array
#385Memory systems having memory devices therein with enhanced error correction capability and methods of operating same
#386Bipolar read retry
#387Error correction circuit of semiconductor memory device and semiconductor memory device including the same
#388Memory with test function and test method thereof
#389Detecting short circuit between word line and source line in memory device and recovery method
#390Partial memory die with masked verify
#391Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits
#392Direct access memory characterization vehicle
#393Ternary content addressable memory (TCAM) for multi bit miss detect circuit
#394Word line driver, semiconductor memory apparatus and test method using the same
#395AC stress methods to screen out bit line defects