SEMICONDUCTOR DEVICE

DETECTION AND COMPENSATION OF TIMING MARGIN ERRORS IN MEMORY

DETECTION AND COMPENSATION OF TIMING MARGIN ERRORS IN MEMORY

PROGRAM REFRESH WITH GATE-INDUCED DRAIN LEAKAGE

UNSELECTED BLOCK LEAKAGE MITIGATION IN A MEMORY DEVICE

APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOF

READ DISTURB SCAN USING FAILED BIT COUNT

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK MEMORY

MEMORY SYSTEM

CONTROLLING MEMORY INCLUDING MANAGING A CORRECTION VALUE TABLE

USING BUILT-IN SELF TEST OR TEST RESULTS TO IDENTIFY WEAK MEMORY BITS AND ENABLE ASSIST CIRCUITS WHEN NECESSARY

3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF OPERATING THE 3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

MEMORY, MEMORY SYSTEM, PROGRAM METHOD OF MEMORY, AND ELECTRONIC APPARATUS

MEMORY

MEMORY DEVICE HAVING CELL OVER PERIPHERY STRUCTURE AND SEMICONDUCTOR DEVICE HAVING BONDING STRUCTURE

DATA CODING DEVICE, MEMORY CONTROLLER, AND STORAGE DEVICE

MEMORY TEST CIRCUIT, MEMORY ARRAY, AND TESTING METHOD OF MEMORY ARRAY

BIT LINE DIRECT CHARGE

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY INPUT/OUTPUT

MEMORY AND OPERATION METHOD THEREOF

MEMORY DEVICE AND MEMORY TEST SYSTEM THEREOF

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES

MEMORY CIRCUIT

DEFECT DETECTION DURING ERASE OPERATIONS

MEMORY FAILURE ANALYSIS BASED ON BITLINE THRESHOLD VOLTAGE DISTRIBUTIONS

METHOD FOR DETECTING AN ERROR IN AN ELECTRONIC MEMORY

MEMORY SYSTEM

MEMORY SYSTEMS HAVING MEMORY DEVICES THEREIN WITH ENHANCED ERROR CORRECTION CAPABILITY AND METHODS OF OPERATING SAME

METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MEMORY REPAIR

SEMICONDUCTOR MEMORY DEVICE, CONTROL METHOD, AND CONTROL DEVICE

STORAGE DEVICE AND DRIVING METHOD OF STORAGE DEVICE

TOPOLOGY-BASED RETIREMENT IN A MEMORY SYSTEM

MEMORY DEVICE AND TEST METHOD THEREOF

Non-volatile memory system with secure detection of virgin memory cells

Memory device performing sensing operation and method of operating the same

Programmable logic device with design for test functionality

APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOF

MEMORY DEVICES AND ELECTRONIC DEVICES OUTPUTING EVENT DATA RELATED TO OCCURRENCES OF ERRORS AND OPERATING METHODS OF MEMORY DEVICES

MEMORY WITH ERROR CHECKING AND CORRECTING UNIT

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK MEMORY

Testing operations for memory systems

Memory test circuit, memory array, and testing method of memory array

SEMICONDUCTOR STORAGE APPARATUS

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

Data coding device, memory controller, and storage device

PROGRAM REFRESH WITH GATE-INDUCED DRAIN LEAKAGE

Non-volatile memory device, operating method thereof, controller for controlling the same, and storage device having the same

APPARATUSES AND METHODS FOR REPAIRING MUTLIPLE BIT LINES WITH A SAME COLUMN SELECT VALUE

Virtualized scan chain testing in a random access memory (RAM) array

OPERATING AND TESTING SEMICONDUCTOR DEVICES

Testability circuit and read and write path decoupling circuit of SRAM

CONTROLLING MEMORY INCLUDING MANAGING A CORRECTION VALUE TABLE

Memory and operation method thereof

METHOD FOR LUT-FREE MEMORY REPAIR

Programmable logic device with design for test functionality

Method and device for checking data, electronic device, and storage medium

Method and apparatus for testing failure of memory, storage medium, and electronic device

Method and device for testing memory chip

METHOD AND DEVICE FOR TESTING MEMORY

Semiconductor memory devices and methods of operating semiconductor memory devices

SEMICONDUCTOR DEVICE AND TESTING METHOD FOR MEMORY CIRCUIT

Memory system

Memory systems having memory devices therein with enhanced error correction capability and methods of operating same

Nonvolatile memory device and method of operating nonvolatile memory

Memory device for column repair

EFFICIENT IMAGE DATA DELIVERY FOR AN ARRAY OF PIXEL MEMORY CELLS

Storage devices and methods of operating storage devices

Defect detection during erase operations

Self-repair for sequential SRAM

Memory and operation method of memory

SYSTEM AND METHOD TO MINIMIZE CODEWORD FAILURE RATE

Circuit and method to detect word-line leakage and process defects in non-volatile memory array

Semiconductor device equipped with global column redundancy

Bipolar read retry

Adjustable programming pulses for a multi-level cell

Method, system and computer program product for memory repair

Methods of testing nonvolatile memory devices

Memory chip having on-die mirroring function and method for testing the same

Memory system

Method for LUT-free memory repair

Non-volatile memory device, operating method thereof, controller for controlling the same, and storage device having the same

Topology-based retirement in a memory system

Storage devices and methods of operating storage devices

Semiconductor memory devices and methods of operating semiconductor memory devices

Non-volatile memory device, controller for controlling the same, storage device having the same, and reading method thereof

Non-volatile memory device, storage device having the same, and reading method thereof

Semiconductor memory devices and memory systems including the same

Memory device for column repair

Memory with error checking and correcting unit

Controlling memory including managing a correction value table

Delay fault testing of pseudo static controls

Memory device and clock locking method thereof

Method and device for fail bit repairing

Fail Bit repair method and device

Defect detecting method and device for word line driving circuit

Non-volatile memory device, operating method thereof, controller for controlling the same, and storage device having the same

Efficient and selective sparing of bits in memory systems

Semiconductor memory devices and methods of operating semiconductor memory devices

Circuit for detecting anti-fuse memory cell state and memory

Error detection and correction using machine learning

Integrated circuit memory with built-in self-test (BIST)

Calibration for integrated memory assembly

Memory and operation method of memory

Method, system and computer program product for memory repair

Memory device

Detection circuitry to detect a deck of a memory array

Memory system for selecting counter-error operation through error analysis and data process system including the same

Method for LUT-free memory repair

Semiconductor memory devices and memory systems

Voltage controller and memory device including same

Memory chip having on-die mirroring function and method for testing the same

Semiconductor memory devices and methods of operating semiconductor memory devices

Circuit and method for at speed detection of a word line fault condition in a memory circuit

Configurable associated repair addresses and circuitry for a memory device

Devices, memory devices, and methods of forming devices

Semiconductor device and operating method thereof

Leaky memory hole repair at fabrication joint

Structure and method for testing three-dimensional memory device

Stacked memory apparatus using error correction code and repairing method thereof

Efficient and selective sparing of bits in memory systems

Error correction for dynamic data in a memory that is row addressable and column addressable

Memory device and test method thereof

Devices, memory devices, and electronic systems

Semiconductor device and operating method thereof

Delay fault testing of pseudo static controls

Layered semiconductor device, and production method therefor

Memory testing method and memory testing system

Memory with a controllable I/O functional unit

Maintaining highest performance of DDR5 channel with marginal signal integrity

Address fault detection in a flash memory system

Memory devices configured to perform leak checks

Efficient and selective sparing of bits in memory systems

Semiconductor storage device, operating method thereof and analysis system

Memory device and test method thereof

Semiconductor device and system including the same

Error detection code hold pattern synchronization

Test circuit block, variable resistance memory device including the same, and method of forming the variable resistance memory device

Memory device performing test on memory cell array and method of operating the same

Semiconductor memory device and test method therefor

Margin test for one-time programmable memory (OTPM) array with common mode current source

Semiconductor device and operating method thereof

Redundancy implementation using bytewise shifting

Memory device and manufacturing method therefor

Semiconductor memory device

Memory with a controllable I/O functional unit

Read disturb detection and recovery with adaptive thresholding for 3-D NAND storage

Structure and method for testing three-dimensional memory device

Memory cell including multi-level sensing

Assessing in-field reliability of computer memories

Error detection code hold pattern synchronization

Apparatuses and methods for controlling wordlines and sense amplifiers

SRAM bitline equalization using phase change material

SRAM bitline equalization using phase change material

Delay fault testing of pseudo static controls

Address fault detection in a flash memory system

Method for low power operation and test using DRAM device

Memory with bit line short circuit detection and masking of groups of bad bit lines

Data storage apparatus and operating method thereof

Fail bit counter and semiconductor memory device having the same

Memory device and operating method thereof

Process variation compensation with correlated electron switch devices

Semiconductor device including control circuit writing data to memory cell

Memory device including column redundancy

Semiconductor memory device and test method therefor

Semiconductor device

Semiconductor memory device and method of operating the same

High speed and low power sense amplifier

Method for screening bad column in data storage medium

Cell current based bit line voltage

Memory devices configured to perform leak checks

Semiconductor storage device and test method thereof using a common bit line

Semiconductor apparatus with reduced risks of chip counterfeiting and network invasion

System for testing charge trap memory cells

Memory device and operating method thereof

Fast soft data by detecting leakage current and sensing time

Semiconductor memory device and test method therefor

Integrated circuit defect detection and repair

Semiconductor storage device and test method thereof using a common bit line

Nonvolatile memory device detecting defective bit line at high speed and test system thereof

Semiconductor device and electronic device

Apparatus and method for detecting and mitigating bit-line opens in flash memory

Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase

Semiconductor memory device

Techniques for determining local interconnect defects

Program operations with embedded leak checks

Test method for memory

Bitline regulator for high speed flash memory system

Side wall bit line structures

Memory hole bit line structures

Controlling adjustable resistance bit lines connected to word line combs

Setting channel voltages of adjustable resistance bit line structures using dummy word lines

Intrinsic vertical bit line architecture

Determination of bit line to low voltage signal shorts

SEMICONDUCTOR MEMORY DEVICE

Short-checking methods

Assist circuits for SRAM testing

Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase

Circuit and data processor with headroom monitoring and method therefor

Semiconductor memory device and method of wafer burn-in test for the same

Methods for accessing a storage unit of a flash memory and apparatuses using the same

Data processing device and manufacturing method thereof

Nonvolatile semiconductor memory apparatus

Semiconductor storage device and test method thereof using a common bit line

Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability

Short-checking methods

Memory with bit line current injection

Memory with redundant sense amplifier

Memory device selecting different column selection lines based on different offset values and memory system including the same

Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase

Temperature compensation of conductive bridge memory arrays

Semiconducotr memory device including non-volatile memory cell array

Semiconductor memory device

Block and page level bad bit line and bits screening methods for program algorithm

Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay

Method of identifying damaged bitline address in non-volatile

Bitline deletion

Bitline deletion

Bitline deletion

Nonvolatile semiconductor memory device

Semiconductor device having hierarchical bit line structure

NAND flash memory employing bit line charge/discharge circuit

Memory with redundant sense amplifier

Memory with bit line current injection

Temperature compensation of conductive bridge memory arrays

Using a precharge characteristics of a node to validate a previous data/signal value represented by a discharge of said node

Semiconductor memory apparatus

Semiconductor memory device and method of testing the same

Fast parallel test of SRAM arrays

Code-based differential charging of bit lines of a sense amplifier

Method of screening static random access memories for pass transistor defects

Device and method for detecting resistive defect

Semiconductor memory device and test method therefor

Memory reliability verification techniques

Test method for screening local bit-line defects in a memory array

TEST CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME, AND TEST METHOD OF THE SEMICONDUCTOR MEMORY APPARATUS

Semiconductor device and control method thereof

Static random access memory (SRAM) and test method of the SRAM having precharge circuit to prepcharge bit line

Programming rate identification and control in a solid state memory

Semiconductor device having bit lines and local I/O lines

Semiconductor device

Semiconductor integrated circuit having a test function for detecting a defective cell

Semiconductor memory device

Scaleable look-up table based memory

Semiconductor integrated circuit with multi test

Memory device having a local current sink

Semiconductor memory device and method for testing the same

Nonvolatile semiconductor memory device

Method and apparatus managing worn cells in resistive memories

Semiconductor device and method for testing the same

Programming rate identification and control in a solid state memory

Bit-line sense amplifier, semiconductor memory device having the same, and method of testing bit-line micro-bridge defect

Semiconductor device and method of detecting abnormality on semiconductor device

Semiconductor memory device and method of testing a sense amplifier of the same

Semiconductor device capable of detecting defect of column selection line

Semiconductor memory device and inspecting method of the same

Test circuit, semiconductor memory apparatus using the same, and test method of the semiconductor memory apparatus

Ripple programming of memory cells in a nonvolatile memory

Bitline precharge voltage generator, semiconductor memory device comprising same, and method of trimming bitline precharge voltage

Semiconductor memory apparatus and test method using the same

Memory device bit line sensing system and method that compensates for bit line resistance variations

Semiconductor device

Semiconductor memory apparatus and test method thereof

Nonvolatile semiconductor memory device

SEMICONDUCTOR MEMORY DEVICE

System for bitcell and column testing in SRAM

Semiconductor memory devices including burn-in test circuits

Semiconductor memory and test method for the semiconductor memory

Integrated circuit memory power supply

SEMICONDUCTOR DEVICE

Semiconductor memory device and test method therefor

Semiconductor memory apparatus and method of testing the same

Semiconductor memory device and methods of performing a stress test on the semiconductor memory device

Bit line bridge detecting method in semiconductor memory device

Bitline leakage detection in memories

Semiconductor memory device

Semiconductor memory device

Method and apparatus for measuring statistics of dram parameters with minimum perturbation to cell layout and environment

Memory having self-timed bit line boost circuit and method therefor

SEMICONDUCTOR MEMORY DEVICE

Semiconductor memory device, test method thereof and semiconductor device

Static random access memory (SRAM) and test method of the SRAM having precharge circuit to precharge bit line

Programming rate identification and control in a solid state memory

Functional float mode screen to test for leakage defects on SRAM bitlines

Memory device bit line sensing system and method that compensates for bit line resistance variations

SEMICONDUCTOR STORAGE DEVICE

Apparatus and method for testing semiconductor memory device

Semiconductor memory device and test method thereof

Semiconductor memory device

Semiconductor integrated circuit with multi test

Semiconductor memory device

Semiconductor memory device and control method

Characterization of bits in a functional memory

SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF

Semiconductor memory device and its test method

SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI TEST METHOD THEREOF

Multi-column decoder stress test circuit

Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance

Memory Circuit, Memory Component, Data Processing System and Method of Testing a Memory Circuit

Semiconductor memory device

Hybrid DRAM